Methods of precise determining the transfer function of picosecond time-to-digital converters

• Autorzy: Sondej Dominik , Szymanowski Rafał , Szplet Ryszard

Identyfikatory

DOI

10.24425/mms.2021.137697

• Języki publikacji: EN

Abstrakty

EN

We present two main ways to precisely create the equivalent transfer function of picosecond time-to-digital converters based on commonly used method with tapped time coding delay lines. The ways consist either in evaluation of the quantization steps boundaries of the delay lines or in summation of numbers of the line quantization steps. The paper contains results of comprehensive analysis of both methods. The advantage and high versatility of the addition method is demonstrated.

Słowa kluczowe

EN

time-to-digital converter; equivalent conversion function; delay line; multi-edge coding; wave-union

• Wydawca: Komitet Metrologii i Aparatury Naukowej PAN
• Czasopismo: Metrology and Measurement Systems
• Rocznik: 2021
• Tom: Vol. 28, nr 3
• Strony: 539--549
• Opis fizyczny: Bibliogr. 13 poz., rys., tab., wykr., wzory

Twórcy

autor

Sondej Dominik

• Military University of Technology, Faculty of Electronics, Institute of Communication Systems, gen. S. Kaliskiego 2, 00-908 Warsaw 46, Poland

autor

Szymanowski Rafał

• Military University of Technology, Faculty of Electronics, Institute of Communication Systems, gen. S. Kaliskiego 2, 00-908 Warsaw 46, Poland

autor

Szplet Ryszard

• Military University of Technology, Faculty of Electronics, Institute of Communication Systems, gen. S. Kaliskiego 2, 00-908 Warsaw 46, Poland

Bibliografia

• [1] Szplet, R., Jachna, Z., Kwiatkowski, P., & Różyc K. (2013). A 2.9 ps equivalent resolution interpolating time counter based on multiple independent coding lines. Measurement Science and Technology, 20(3), 1-15. https://doi.org/10.1088/0957-0233/26/7/075002
• [2] Wu, J., & Shi, Z. (2008). The 10-ps wave union TDC: Improving FPGA TDC resolution beyond its cel delay. Proceedings of the IEEE Nuclear Science Symposium Conference Record, Dresden. 3440-3446. https://lss.fnal.gov/archive/2008/conf/fermilab-conf-08-498-e.pdf
• [3] Szplet, R. (2014). Time-to-digital converters. In Carbone P., Kiaei, S., & Xu, W. (Eds.). Design, Modeling and Testing of Data Converters (pp. 211-246). Springer-Verlag. https://doi.org/10.1007/978-3-642-39655-7_7
• [4] Cova, S. & Bertolaccini, M. (1970). Differential linearity testing and precision calibration of multi-channel time sorters. Nuclear Instruments and Methods, 77(2), 269-276.
• [5] Szplet, R., Szymanowski, R., & Sondej, D. (2019). Measurement Uncertainty of Precise Interpolating Time Counters. IEEE Transactions on Instrumentation and Measurement, 68(11), 4348-4356. https://doi.org/10.1109/TIM.2018.2886940
• [6] Frankowski, R., Chaberski, D., & Kowalski, M. (2015). An optical method for the time-to-digital converters characterization. Proceedings of the International Conference on Transparent Optical Networks, Budapest. https://doi.org/10.1109/ICTON.2015.7193659
• [7] Rivoir J. (2006). Statistical Linearity Calibration of Time-to-Digital Converters Using a Free-Running Ring Oscillator. Proceedings of the 15th Asian Test Symposium, Fukuoka, Japan. 45-50. https://doi.org/10.1109/ATS.2006.260991
• [8] Chaberski, D., Frankowski, R., Gurski, M., & Zieliński, M. (2017). Comparison of interpolators used for time-interval measurement systems based on multiple-tapped delay line. Metrology and Measurement Systems, 24(2), 401-412.
• [9] Mota, M. (2000). Design and Characterization of CMOS High-Resolution TDCs. [Doctoral dissertation, Inst. Superior Técnico, Tech. Univ. of Lisbon].
• [10] Wu, J. (2014). Uneven Bin Width Digitization and a Timing Calibration Method Using Cascaded PLL. Proceedings of 19th IEEE-NPSS Real-Time Conference 2014, Japan
• [11] Xie, W., Chen, H., & Li, D. D. U. (2021). Efficient time-to-digital converters in 20 nm FPGAs with wave union. IEEE Transactions on Industrial Electronics (Early Access). https://doi.org/10.1109/TIE.2021.3053905
• [12] Frankowski, R., Gurski, M., & Płóciennik, P. (2016). Optical methods of the delay cells characteristics measurements and their applications. Optical and Quantum Electronics, 48, 188. https://doi.org/10.1007/s11082-016-0465-6
• [13] Kalisz, J., Orzanowski, T., & Szplet, R. (2000). Delay-locked loop technique for temperature stabilisation of internal delays of CMOS FPGA devices. Electronics Letters, 36(14), 1184-1185

Uwagi

1. This work was supported by the Military University of Technology under research project UGB 851.

2. Opracowanie rekordu ze środków MNiSW, umowa Nr 461252 w ramach programu "Społeczna odpowiedzialność nauki" - moduł: Popularyzacja nauki i promocja sportu (2021).