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Scaling of signed residue numbers with mixed-radix conversion in FPGA with extended scaling factor selection

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Warianty tytułu
Języki publikacji
EN
Abstrakty
EN
A scaling technique of signed residue numbers in FPGA is proposed. The technique is based on conversion of residue numbers to the Mixed-Radix System (MRS). The scaling factor is assumed to be a moduli product from the Residue Number System (RNS) base. Scaling is performed by scaling of MRS terms, the subsequent generation of residue representations of scaled terms, binary addition of these representations and generation of residues for all moduli. The sign of the residue number is detected by using the most significant digit of the MRS representation. Basic blocks of the scaler are realized in the form of modified two-operand modulo adders with included additional multiply and modulo reduction operations. An exemplary pipelined realization of the scaler in the Xilinx FPGA environment is shown. The design is based on Look-Up Tables (LUT)(2,sup>6 x 1) that simulate small RAMs which serve as main components for the look-up realization. Also a method is shown that allows for flexible selection of scaling factors from a set of moduli products of the RNS base. This is made by forming auxiliary MRSs by permutation of moduli of the base. All formed MRSs are associated with the given RNS with respect to the base but each MRS has different set of weights. Thus for the required scaling factor, the suitable MRS can be chosen that provides for the scaling error smaller than 1.
Rocznik
Tom
Strony
465--477
Opis fizyczny
Bibliogr. 18 poz., rys.
Twórcy
autor
  • University of Technology, 80-233 Gdańsk, ul. Narutowicza 11/12
autor
  • University of Technology, 80-233 Gdańsk, ul. Narutowicza 11/12
autor
  • University of Technology, 80-233 Gdańsk, ul. Narutowicza 11/12
Bibliografia
  • [1] Szabo N.S, R.J., Tanaka R.J., Residue Arithmetic and its Applications to Computer Technology. New York, McGraw-Hill, 1967.
  • [2] Soderstrand M. et al, Residue Number System Arithmetic: Modern Applications in Digital Signal Processing. IEEE Press, NY, 1986.
  • [3] Omondi A., Premkumar B.: Residue Number Systems: Theory and Implementation. London, Imperial College Press, 2007.
  • [4] Xilinx, Virtex-7, www.xilinx.com.
  • [5] Jullien G.A.: Residue number scaling and other operations using ROM arrays. IEEE Trans. on Computers, Vol. C-27, pp. 325-336, April 1978.
  • [6] Jenkins W.: Recent advances in residue number techniques for recursive digital filtering. IEEE Trans. on Acoust., Speech and Signal Processing, Vol. 27, pp. 19-30, Feb. 1979.
  • [7] Taylor F.J., Huang C.H.: An autoscale residue multiplier, IEEE Trans. on Computers, Vol. C-31, pp. 321-325, April 1982.
  • [8] Miller D.D., Polky J.N.: An implementation of the LMS algorithm in the residue number system. IEEE Trans. on Circuits and Systems, Vol. 31, pp. 452-461. May 1984.
  • [9] Shenoy M.A.P., Kumaresan R.: A fast and accurate RNS scaling technique for highspeed signal processing. IEEE Trans. Acoust. Speech, Signal Processing, Vol. 37, pp. 929-937, June 1989.
  • [10] Griffin M., Sousa M., Taylor F.: Efficient scaling in the residue number system. Proc. of Int. Conf. on Acoustics, Speech and Signal Processing 1989, pp. 1075-1078.
  • [11] Ulman Z.D., Czyżak M.: Highly parallel fast scaling of numbers in nonredundant residue arithmetic. IEEE Trans. on Signal Processing, Vol. 46, pp. 487-496, Feb. 1998.
  • [12] Garcia A., Lloris A.: A look-up scheme for scaling in the RNS. IEEE Trans. on Computers, Volume 48, pp. 748-751, July 1999.
  • [13] Meyer-Baese U., Stouraitis T.: New power-of-2 RNS scaling scheme for cell based IC design. IEEE Trans. on Large Scale Integration(VLSI) Systems, Vol. 11, No.4, 2003, pp. 280-283.
  • [14] Kong Y., Phillips B.: Fast scaling in residue number system. IEEE Trans. on Large Scale Integration(VLSI) Systems, Vol. 17, No.3, March 2009, pp. 443-447.
  • [15] Ma S., Hu J.H., Zhang L., Ling X.: A 2n scaling scheme for signed RNS integers and its VLSI Implementation. Science China: Informations Sciences, Vol. 53, No. 1, pp. 203-212.
  • [16] Lu M., Chiang J.S.: A novel division algorithm for the residue number system. IEEE Trans. on Computers, Vol. 41, No.8, 1992, pp. 1026-1032.
  • [17] Burgess N.: Scaling an RNS number using the core function. 16th IEEE Symposium on Computer Arithmetic 2003, Santiago de Compostela, Spain, pp. 262-269, 2003.
  • [18] Ulman Z., Czyżak M.: Scaling of numbers with implicit sign in residue arithmetic. XIXth National Conf. Circuit Theory and Electronic Networks, Vol. 2, pp. 505-510, 1996.
Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-71dc2ad5-c35b-42c8-8d95-61774760fcac
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