FPGA implementation of reverse residue conversion based on the new Chinese Remainder Theorem II- Part I

• Autorzy: Ulman Z. , Czyżak M. , Smyk R.
• Konferencja: Computer Applications in Electrical Engineering 2012 (23-24.04.2012; Poznań, Polska)
• Języki publikacji: EN

Abstrakty

EN

This work describes a derivation and an implementation of the algorithm of conversion from the Residue Number System (RNS) to the binary system based on the new form of the Chinese Remainder Theorem (CRT) termed the New CRT II. The new form of the CRT does not require the modulo M operation, where M is the residue number system range, but a certain number of multipliers is needed. Because in the FPGA environments the multipliers or the special DSP blocks are available, so they can be used in the converter realization. The main aim of the work is to examine experimentally the needed hardware amount and the influence of the multipliers on the maximum pipelining frequency. In Part I the derivation of the conversion algorithm is described. In Part II the hardware implementation of the converter in the FPGA technology is shown.

Słowa kluczowe

EN

FPGA; Residue Number System; RNS; Chinese remainder theorem; CRT; New CRT II

• Wydawca: Wydawnictwo Politechniki Poznańskiej
• Czasopismo: Poznan University of Technology Academic Journals. Electrical Engineering
• Rocznik: 2012
• Tom: No. 71
• Strony: 133--138
• Opis fizyczny: Bibliogr. 13 poz.

Twórcy

autor

Ulman Z.

• Gdansk University of Technology

autor

Czyżak M.

• Gdansk University of Technology

autor

Smyk R.

• Gdansk University of Technology

Bibliografia

• [1] A. Svoboda, "Rational numerical system of residual classes", Stroje na Zpracovani Informaci, Sbornik V, Nakl. CSAV, s.9-37, Praha 1957.
• [2] A. Svoboda, M. Valach,. The numerical system of residual classes in mathematical machines, Proc. Congr. Int. Automa, 1958.
• [3] N.S. Szabo and R.J. Tanaka, Residue Arithmetic and its Applications to Computer Technology, New York, McGraw-Hill, 1967.
• [4] M. Soderstrand et al., Residue Number System Arithmetic: Modern Applications in Digital Signal Processing, IEEE Press, NY, 1986.
• [5] A. Omondi, B. Premkumar, Residue Number Systems: Theory and Implementation, London, Imperial College Press, 2007.
• [6] S.J.Piestrak, Design of residue generators and multioperand modulo adders using carry-save adders, IEEE Trans. Comp., Vol. 43, Jan. 1994, pp. 68-77.
• [7] K.M. Elleithy , M.A. Bayoumi, Fast and flexible architectures for RNS arithmetic decoding, IEEE Trans, on Circuits and Systems-II: Analog and Digital Signal Processing, Vol. 39, no. 4, April 1992, pp. 226-235.
• [8] Z. Wang Z., G.A. Jullien , W.C. Miller , An Improved Residue-To-Binary Converter, IEEE Trans. Circuits Syst.-I: Fundamental Theory and Applications, Vol. 47, September 2000, pp. 1437-1440.
• [9] S.J. Meehan, S.D. O’Neil , J.J. Vaccaro, An Universal Input And Output Converter, IEEE Trans. Circuit Syst., Vol. CAS-37, June 1990, pp. 1158-1162.
• [10] N. Burgess, Scaled And Unsealed Residue Number System To Binary Conversion Techniques Using The Core Function, 1997 IEEE Symposium on Computer Arithmetic, pp. 250-257.
• [11] G.C. Cardarilli , M. Re , R. Lojacono , A Systolic Architecture For High Performance Scaled Residue To Binary Conversion, IEEE Trans. Circuits Syst. -I: Fundamental Theory And Applications, Vol. 47, October 2000, pp.667-669.
• [12] M.Czyżak, An improved high-speed residue-to-binary converter based on the Chinese Remainder Theorem, Pomiary Automatyka Kontrola, Vol. 53, no.4, April 2007, pp.72-75.
• [13] Y. Wang, Residue-to-binary Converters Based On the new Chinese Remainder Theorems, IEEE Trans. Circuits and Systems-II: Analog and Digital Signal Processing, VI. 47, No. 4, September 2000, pp.197-205.