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Tytuł artykułu

1.25GS/S 12bit and 2.27mW digital to analog converter (DAC) with 70.22 SNDR based on new hybrid R-C procedure in 180nm CMOS

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Języki publikacji
EN
Abstrakty
EN
This paper presents a novel fully differential high-speed and high-resolution Digital to Analog Converter (DAC) based on new reliable hybrid R-C technique. In the proposed idea the four LSB bits and eight MSB bits are implemented as a resistor string and new merged capacitor technique respectively. Applying the suggested method the SNDR and Effective Number of Bits (ENOB) of the proposed DAC achieve 70.22dB and 11.41 bit at the 1.25GS/s sampling rate correspondingly. In the proposed method the total capacitors of the 8 MSB bits are reduced up to 78% compared to the conventional one noticeably. As a result, the power consumption and speed of the suggested DAC are decreased and increased respectively. Moreover, the total power consumption of the proposed DAC is 2.27mW with the power supply of 1.8 volts as well. Meanwhile, for the correctness of the proposed 12bit DAC, 200 iterations in transient Monte-Carlo analysis (parasitic capacitance included ([symbol] mismatch = 1.2%)), and the SNDR simulation results versus different input frequency at fS=1.25GS/s sampling rate are applied too. The maximum Integral Nonlinearity (INL) and the maximum Differential Nonlinearity (DNL) are -0.47/+0.35LSB and -0.42/+0.29 LSB respectively. The proposed DAC structure is simulated in all process corners and performed using the HSPICE BSIM3 model of a 0.18μm CMOS technology.
Rocznik
Strony
127--132
Opis fizyczny
Bibliogr. 29 poz., il. kolor., rys., wykr.
Twórcy
autor
  • 1Young Researchers and Elite Club, Tabriz Branch, Islamic Azad University, Tabriz, Iran
autor
  • Department of Microelectronics Engineering, Urmia Graduate Institute, Urmia, Iran
autor
  • Department of Microelectronics Engineering, Urmia Graduate Institute, Urmia, Iran
  • Department of Microelectronics Engineering, Urmia Graduate Institute, Urmia, Iran
autor
  • Department of Microelectronics Engineering, Urmia Graduate Institute, Urmia, Iran
Bibliografia
  • [1] X. Li, Q. Wei, Z. Xu, J. Liu, H. Wang, H. Yang, "A 14 Bit 500 MS/s CMOS DAC Using Complementary Switched Current Sources and Time-Relaxed Interleaving DRRZ", IEEE Transactions on Circuits and Systems I: Regular Papers, vol.61, 2014, pp. 2337 - 2347.
  • [2] S. Mahdavi, "A 12 bit 76MS/s SAR ADC with a Capacitor Merged Technique in 0.18um CMOS Technology", Journal of Electrical and Computer Engineering Innovations (JECEI), 2017, vol.5, issue.2, pp. 4-4.
  • [3] W. Jin Eom, K. Kwon, K. Lee, J. Joon Kim, "A Supply-Scalable Dual-Rate Dual-Mode DAC with an Adaptive Swing Control", IEEE Transactions on Circuits and Systems II: Express Briefs, vol. PP, 2017, pp. 1-1.
  • [4] S. Mahdavi, et. al., "A New 13-bit 100MS/s Full Differential Successive Approximation Register Analog to Digital Converter (SAR ADC) Using a Novel Compound R-2R/C Structure ", 4th International Conference on Knowledge-Based Engineering and Innovation (KBEI-2017), 2017, in press.
  • [5] W. Lin, T. Kuo, "A 12b 1.6GS/s 40mW DAC in 40nm CMOS with >70dB SFDR over entire Nyquist bandwidth", 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers, 2013, pp: 474 - 475.
  • [6] A. Baradaran Rezaeii, S. Mahdavi, A. Amini, T. Aspokeh and M. Poreh "A New High Resolution Calibration Technique Based on Counter- DAC Combination to Eradicate Mismatch Effect of the Current Sources in 0.18um CMOS", 3rd International Conference on Engineering and Applied Sciences, September 2016.
  • [7] Y. Tang, J. Briaire, K. Doris, R. van Veldhoven, P. van Beek, H. Hegt, A. van Roermund, "A 14b 200MS/s DAC with SFDR>78dBc, IM3<-83dBc and NSD<-163dBm/Hz across the whole Nyquist band enabled by dynamic mismatch mapping," IEEE Journal of Solid-State Circuits, 2011, vol.46,pp: 1371 -1381.
  • [8] C-H. Lin, F. van der Goes, J. Westra, J. Mulder, Y. Lin, E. Arslan, E. Ayranci, X. Liu, K. Bult, "A 12b 2.9GS/s DAC with IM3 « -60d6c beyond 1GHz in 65nm CMOS," ISSCC, 2009, pp: 74 - 75,75a.
  • [9] L. Chih-Wen, H. Ching-Min, L. Yo-Sheng, and M. C. F. Chang, "A 10-Bit DAC With 1.6-Bit Interpolation Cells for Compact LCD 50ns Column Driver ICs," Display Technology, Journal of, vol. 9, pp. 176-183, 2013.
  • [10] Kh. Hadidi, "Data Converter Course Notes" Urmia University, Urmia, Iran, 2005.
  • [11] M. Kim, Y. Kim, Y. Kwak, G. Ahn ,"A 12-bit 200-kS/s SAR ADC with hybrid RC DAC", Proceedings of the IEE 2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2014, pp: 185 - 188.
  • [12] H. Deng, P. Li, "A 8-bit 10MS/s asynchronous SAR ADC with resistor-capacitor array DAC", 2014 International Conference on Anti-Counterfeiting, Security and Identification (ASID)), 2014, pp: 1 - 5.
  • [13] L. Yu, J. Zhang, L. Wang, J. Lu, "A 12-bit fully differential SAR ADC with dynamic latch comparator for portable physiological monitoring applications", 2011 4th International Conference on Biomedical Engineering and Informatics (BMEI), 2011, pp: 576 - 579.
  • [14] Y. Li, D. Chen, "A novel 20-bit R-2R DAC structure based on ordered element matching", 2015 IEEE International Symposium on Circuits and Systems (ISCAS), 2015, pp: 1030 - 1033.
  • [15] S. Salem, A. Hakimi, "A modified folded multi-LSB decided resistor string digital to analog converter", 2016 24th Iranian Conference on Electrical Engineering (ICEE), 2016, pp: 148 - 151.
  • [16] W. Xiong, Y. Guo, U. Zschieschang, H. Klauk, B. Murmann, "A 3-V, 6-Bit C-2C Digital-to-Analog Converter Using Complementary Organic Thin-Film Transistors on Glass", IEEE Journal of Solid-State Circuits, 2010, Vol.45, Issue7, pp: 1380 - 1388.
  • [17] L. Cong, "Pseudo C-2C Ladder-Based Data Converter Technique," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process, 2001, vol. 48, no. 10, pp. 927-929.
  • [18] S. Mahdavi, R. Ebrahimi, A. Daneshdoust, A. Ebrahimi, "A 12bit 800MS/S and 1.37mW Digital to Analog Converter (DAC) Based on Novel R-C Technique," IEEE International Conference on Power, Control, Signals and Instrumentation Engineering (ICPCSI-2017), in press.
  • [19] H. Kim, Y. Min, Y. Kim, and S. Kim, "A Low Power Consumption 10-bit Rail-to-Rail SAR ADC Using a C-2C Capacitor Array," IEEE Int. Conf. on EDSSC, 2008, pp. 1-4.
  • [20] S.-W. Lee, H.-J. Chung and C.-H. Han, "C-2C Digital-to-Analogue Converter on Insulator," IEEE Electron. Lett, vol. 35, no. 15, pp. 1242-1243.
  • [21] E. Ansari, D. Wentzloff, "A 5mW 250MS/s 12-bit synthesized digital to analog converter", Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014, pp: 1-4.
  • [22] B. Ma, Q. Huang, Fengqi Yu, "A 12-bit 1.74-mW 20-MS/s DAC with resistor-string and current-steering hybrid architecture", 2015 28th IEEE International System-on-Chip Conference (SOCC), 2015, pp: 1 - 6.
  • [23] S. Mahdavi, K. Hadidi "A 14 bit 17 MS/s 80dB SNDR Low Power SAR ADC With Energy-Efficient Switching Procedure", unpublished.
  • [24] Z. Jaworski, "A highly linear 4-bit DAC with 1 GHz sampling rate implemented in 28 nm FD-SOI process", 2017 MIXDES - 24th International Conference "Mixed Design of Integrated Circuits and Systems, 2017, pp: 189-195.
  • [25] J. Pirkkalaniemi, M. Waltari, M. Kosunen, L. Sumanen, K. Halonen, "Current mode deglitcher for current-steering DACs", Proceedings of the 28th European Solid-State Circuits Conference, 2002, pp: 479 - 482.
  • [26] S.Tse Chiou, "A 1.2-V 14-bit 300-MHz current-steering DAC with transimpedance output", 2017 International Conference on Applied System Innovation (ICASI), 2017, pp: 512 - 514.
  • [27] A. Kumar Baranwal, Anurag, B. Singh, "Design and Analysis of 8 Bit Fully Segmented Digital to Analog Converter", 2015 2nd International Conference on Recent Advances in Engineering & Computational Sciences (RAECS), 2015, pp: 1-4.
  • [28] Y.-M. Liao and T.-C. Lee, "A 6-b 1.3Gs/s A/D Converter with C-2C Switch-Capacitor Technique," IEEE Int. Symp. On VLSI-DAT, 2006, pp. 1-4.
  • [29] Kh. Hadidi, A. Khoei, "A highly linear cascode-driver CMOS source-follower buffer", Proceedings of Third International Conference on Electronics, Circuits, and Systems, 1996, pp: 1243 - 1246.
Uwagi
Opracowanie rekordu w ramach umowy 509/P-DUN/2018 ze środków MNiSW przeznaczonych na działalność upowszechniającą naukę (2018).
Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-712f300b-1d2a-4b75-941b-daebce24b0e6
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