The window comparator circuit with CMOS and TTL logic ics switching levels

• Autorzy: Boonkirdram Sarawoot , Sonasang Somchat , Summatta Chuthong

Identyfikatory

DOI

10.15199/48.2024.01.23

Warianty tytułu

PL

Obwód komparatora okiennego z poziomami przełączania układów logicznych CMOS i TTL

• Języki publikacji: EN

Abstrakty

EN

The digital window comparator circuits with digital switching levels use different threshold voltages. The proposed circuit consists of a Schmitt-trigger inverter gate and the AND gate. Both gates have different switch levels, and the circuit has a window boundary between both threshold voltages. The input voltages range between the threshold levels, and the output logic is "High". The input voltage is higher or lower than the range, and the output logic is "Low". This paper presents the coupling of different types of logic ICs for the development of digital window comparator circuits, the simulation results, and the experimental circuit results that create a window boundary between VIL(D) < Vin < VIH(R).

PL

Obwody cyfrowego komparatora okienkowego z cyfrowymi poziomami przełączania wykorzystują różnicowe napięcia progowe. Proponowany układ składa się z bramki falownika z wyzwalaczem Schmitta i bramki AND. Obie bramki mają różne poziomy przełączania, a obwód ma granicę okna między obydwoma napięciami progowymi. Napięcia wejściowe mieszczą się w zakresie między poziomami progowymi, logika wyjściowa jest „wysoka”. Napięcie wejściowe jest wyższe lub niższe niż zakres, logika wyjściowa jest „niska”. W artykule przedstawiono sprzężenie różnych typów logicznych układów scalonych w celu opracowania obwodów cyfrowego komparatora okienkowego, wyniki symulacji oraz wyniki obwodów eksperymentalnych, które tworzą granicę okna między VIL(D) < Vin < VIH(R).

Słowa kluczowe

EN

window comparator; digital switching levels; voltage detector; window boundary

PL

komparator okienkowy; cyfrowy poziom przełączania; detektor napięcia; granica okienkowa

• Wydawca: Wydawnictwo SIGMA-NOT
• Czasopismo: Przegląd Elektrotechniczny
• Rocznik: 2024
• Tom: R. 100, nr 1
• Strony: 112--116
• Opis fizyczny: Bibliogr. 17 poz., rys., tab.

Twórcy

autor

Boonkirdram Sarawoot

• Program of Electrical and Electronics, Faculty of Industrial Technology, Sakon Nakhon Rajabhat University, Sakon Nakhon, Thailand

• https://orcid.org/0000-0001-9907-7339

autor

Sonasang Somchat

• Department of Industrial Technology, Faculty of Industrial Technology, Nakhon Phanom University, Nakhon Phanom, Thailand

• https://orcid.org/0000-0002-3261-4547

autor

Summatta Chuthong

• Department of Industrial Technology, Faculty of Industrial Technology, Nakhon Phanom University, Nakhon Phanom, Thailand

• https://orcid.org/0000-0003-3276-6580

Bibliografia

• [1] K. Futsuhara, and M. Mukaidono, "Application of Window Comparator to Majority Operation," The Nineteenth International Symposium on Multiple-Valued Logic, 1989, pp. 114-121.
• [2] M. Sakai, M. Kato, K Futsuhara, and M. Mukaidono, "Application of Fail-safe Multiple-valued Logic to Control of Power Press," International Symposium on Twenty-Second Multiple-Valued Logic, 1992, pp. 271-350.
• [3] K. Futsuhara, and M. Mukaidono, "A Realisation of Fail-safe Sensor Using Electromagnetic Induction," Conference on Precision Electromagnetic Measurements CPEM 88 Digest, 1988, pp. 99-100.
• [4] S. Deeon, Y. Hirao and K. Tanaka, "A Relay Drive Circuit for a Safe Operation Order and its Fail-safe Measures," The journal of Reliability Engineering Association of Japan. Japan, vol. 34, No.7, 2012. pp. 489-500.
• [5] S. Deeon, Y. Hirao, and K. Futsuhara, "A Fail-safe Counter and its application to Low-speed Detection," Transaction of Reliability Engineering Association of Japan, vol.33, No.3, 2011, pp.137-146.
• [6] V. A. Pedroni, "Low-voltage high-speed Schmitt trigger and compact window comparator," Electronics Letters, Vol. 41, No. 22, 2005, pp. 1213–1214.
• [7] P. Sagar, and M. Panicker P. R., "A Novel, High Speed Window Comparator Circuit," International Conference on Circuits, Power and Computing Technologies (ICCPCT), 2013, pp. 691-693.
• [8] C. Summatta, and S. Deeon, "A Window Comparator Circuit with Digital Switching Levels," The 9th International Conference on Sciences, Technology and Innovation for Sustainable Well-Being (STISWB 2017), Kunming University of Sciences and Technology, 2017, pp. 74-78.
• [9] C. Summatta, T. Phurahong, W. Rattanangam, and W. Chaiyong, "Low-cost and Compact Window Comparator Circuit with MOSFET-Resistor Voltage References," IEEE 2nd International Conference on Power and Energy Applications (ICPEA 2019), Singapore, 2019, pp. 75-78.
• [10] C. Summatta, T. Phurahong, "Three-Stage Window Comparator Circuit with MOSFET-Resistor Voltage Reference" 2020 3rd International Conference on Power and Energy Applications (ICPEA), Busan, Korea (South), 2020, pp.37-40.
• [11] C. Summatta, W. Khamsen, A. Pilikeaw, S. Deeon. "Design and Analysis of 2-out-of-3 Voters Sensing in Electrical Power Drive System" in Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology (ECTI-CON 2016); Thailand; 2016.
• [12] C. Summatta, S. Deeon, "Design and Analysis of 2oo3 Static Voter for SMT function in an Adjustable Speed Electrical Power Drive System," Journal of Telecommunication, Electronic and Computer Engineering (JTEC), Vol.11, No.1, 2019, pp.1-6.
• [13] C. Summatta, W. Rattanangam, "The improvement of a fail-safe counter for low-speed detection" Przegląd Elektrotechniczny, Vol.97, No.7, 2021, pp.23-28.
• [14] C. Summatta and S. Deeon, "Simple anti capacitor open-circuit self-oscillation in a CMOS schmitt trigger-invertor oscillator circuit." Przeglad Elektrotechniczny. Vol. 95, No.3. Mar 2019. pp. 97–100.
• [15] C. Summatta, and S. Sonasang, "Safety analysis of 2-pin capacitor as 4-pin capacitor with frequency response" Creative Science, Vol. 14, No.3, 2022. pp. 1-6.
• [16] Logic Guide 2017, Texas Instruments Incorporated, www.ti.com/logic.
• [17] https://www.allaboutcircuits.com/textbook/digital/chpt-3/logic-signal-voltage-levels/.

Uwagi

Opracowanie rekordu ze środków MNiSW, umowa nr POPUL/SP/0154/2024/02 w ramach programu "Społeczna odpowiedzialność nauki II" - moduł: Popularyzacja nauki i promocja sportu (2025).