A low-jitter, full-differential PLL in 0.18μm CMOS technology

• Autorzy: Modarresi F. , Ghasemzadeh M. , Mazlumi M. , Amini A. , Abolfathi T.
• Języki publikacji: EN

Abstrakty

EN

This paper presents a Phase Locked Loop (PLL) which works with minimum jitter in the operation frequency range of 600MHZ to 900MHZ. Utilizing a full differential architecture that consists of several blocks of differential VCO, a differential PFD and a differential CPL leads to limiting the RMS jitter to 4.06ps, with 50mV power supply noise in the frequency range of 750MHz. Simulation results using 0.18μm CMOS TSMC standard technology demonstrate the power-consumption of 4.6mW at the supply voltage of 1.8V.

Słowa kluczowe

EN

full differential PLL; PFD; VCO; low jitter; CPL

PL

pętla synchronizacji fazy; PLL; VCO; generator sterowany napięciem; niski jitter; CPL

• Wydawca: Lodz University of Technology. Department of Microelectronics and Computer Science
• Czasopismo: International Journal of Microelectronics and Computer Science
• Rocznik: 2016
• Tom: Vol. 7, nr 4
• Strony: 119--122
• Opis fizyczny: Bibliogr. 10 poz., rys., wykr.

Twórcy

autor

Modarresi F.

• Department of Microelectronics Engineering, Urumi Graduate Institute, Urmia, Iran

autor

Ghasemzadeh M.

• Department of Microelectronics Engineering, Urumi Graduate Institute, Urmia, Iran

autor

Mazlumi M.

• Department of Microelectronics Engineering, Urumi Graduate Institute, Urmia, Iran

autor

Amini A.

• Department of Microelectronics Engineering, Urumi Graduate Institute, Urmia, Iran

autor

Abolfathi T.

• Department of Microelectronics Engineering, Urumi Graduate Institute, Urmia, Iran

Bibliografia

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• [2] Chun-Huat Heng; Bang-Sup Song, „A 1.8 GHz CMOS fractional-N frequency synthesizer with randomized multi-phase VCO,” Custom Integrated Circuits Conference, 2002. Proceedings of the IEEE 2002 , vol., no., pp.427,430, 2002.
• [3] Bhavana Goyal, Shruti Suman, P. K. Ghosh, Design of Charge Pump PLL using Improved Performance Ring VCO” International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT) -2016.
• [4] B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw Hill. 2001.
• [5] B. Razavi, Monolithic Phase-Locked Loops and Clock Recovery Circuits, IEEE Press, 2003
• [6] M. Ghasemzadeh, A. Akbari, N. Mohabbatian, Kh. Hadidi and A. Khoei, „A novel method in fractional synthesizers for a drastic decrease in lock time,” Mixed Design of Integrated Circuits & Systems (MIXDES), 2014 Proceedings of the 21st International Conference, Lublin, 2014, pp.138-141.
• [7] I. Hwang, S. Lee, S. Lee, and S. Kim, „A digitally controlled phase locked loop with fast locking scheme for clock synthesis application,” ISSCC Dig. Tech. Papers, pp. 168-169, Feb. 2000.
• [8] D. W. Boerstler, „A low-jitter PLL clock generator for microprocessors with lock range of 340-612 MHz,” IEEE J. Solid State Circuits, vol. 34, pp. 513-519, Apr. 1999.
• [9] M. Ghasemzadeh, S. Mahdavi, A. Zokaeiand K. Hadidi, „A new adaptive PLL to reduce the lock time in 0.18um technology,” 2016MIXDES - 23rd International Conference Mixed Design of Integrated Circuits and Systems, Lodz, 2016, pp. 140-142.
• [10] M. Ghasemzadeh, A. Soltani, A. Akbari and K. Hadidi, „Fast and accurate fractional frequency synthesizer in 0.18um technology,” 2015 22nd International Conference Mixed Design of Integrated Circuits & Systems (MIXDES 2015), Torun, 2015, pp. 330-333.