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The flying-capacitor SEPIC converter with the balancing circuit

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Języki publikacji
EN
Abstrakty
EN
The paper presents investigation results of the natural balancing phenomena in the flying-capacitor SEPIC converters. The SEPIC converters topologies can be reconfigured to the flying-capacitor topology. Owing to this modification the advantageous increase of frequency of the current in the chokes and the decrease of semiconductors voltages can be achieved which is shown in this paper. Similarly to other multilevel flying capacitor topologies the adequate voltage sharing of the flying capacitors is an important issue for safe operation of the converter. The paper focuses on the analysis of the flying capacitor voltages balancing in the converter by natural currents as well as by the application of the additional RLC balancing booster. The paper proves that the natural balancing can be achieved by the specific application of the balancing circuit in the flying-capacitor SEPIC topology and proves the specific differences in the balancing process by natural currents of converter and with the usage of the balancing circuit. An operation of the converter with the balancing circuit and the natural balancing ability is studied here.
Słowa kluczowe
Rocznik
Strony
411--424
Opis fizyczny
Bibliogr. 27 poz., fig., tab., wz.
Twórcy
autor
  • AGH University of Science and Technology Department of Power Electronics and Energy Control Systems Mickiewicza 30, 30-059 Kraków
autor
  • AGH University of Science and Technology Department of Power Electronics and Energy Control Systems Mickiewicza 30, 30-059 Kraków
Bibliografia
  • [1] Stala R., The Switch-Mode Flying-Capacitor DC–DC Converters With Improved Natural Balancing, IEEE Transactions on Industrial Electronics 57: 1369-1382 (2010).
  • [2] Ruan X., Wei J., Xue Y., Three-level converters with the input and output sharing the ground, Power Electronics Specialist Conference PESC'03, IEEE 34th Annual 4: 1919-1923 (2003).
  • [3] Ruan X., Li B., Chen Q., Three-level converters A new approach in high voltage dc-to-dc conversion, Power Electronics Specialists Conference, PESC’02. 2002 IEEE 33rd Annual 2: 663-668 (2002).
  • [4] Ruan X., Li B., Chen Q., Tan S-C., Tse C.K., Fundamental Considerations of Three-Level DC-DC Converters: Topologies, Analyses and Control, IEEE Transactions on Circuits and Systems I: Regular Papers 55: 3733-3743 (2008).
  • [5] Jin K., Ruan X., Zero-Voltage-Switching Multiresonant Three-Level Converters, IEEE Transaction on Industrial Electronics 54: 1705-1715 (2007).
  • [6] Forest F., Meynard T. A., Faucher S., Richardeau F., Huselstein J-J, Joubert C., Using the Multilevel Imbricated Cells Topologies in the Design of Low-Power Power-Factor-Corrector Converters, IEEE Transactions on Industrial Electronics 52: 151-161 (2005).
  • [7] Francois B., Hautier J. P., Multilevel Structures for Four-Level DC/DC Voltage Conversions: Enhanced Analysis and Control Design Issues, Power Electronics Specialists Conference, PESC’02. 2002 IEEE 33rd Annual 2: 932-937 (2002).
  • [8] Janke W., The description methods of DC-DC power converters, Przegląd Elektrotechniczny 88(11b): 5-10 (2012) (in Polish).
  • [9] Kawa A., Penczek A., Piróg S., DC-DC boost-flyback converter functioning as input stage for one phase low power grid-connected inverter, Archives of Electrical Engineering 63(3): 393-407, ISSN: 2300-2506 (2014).
  • [10] Janke W., Averaged models of pulse-modulated DC-DC power converters. Part I. Discussion of standard methods, Archives of Electrical Engineering 61(4): 609-631 (2012).
  • [11] Janke W., Averaged models of pulse-modulated DC-DC power converters. Part II. Models based on the separation of variables. Archives of Electrical Engineering 61(4): 633-654 (2012).
  • [12] Penczek A., Stala R., Stawiarski Ł., Szarek M., Hardware-in-the-Loop FPGA-based Simulations of Switch – mode Converters for Research and Eucational Purposes, Przegląd Elektrotechniczny 87(11): 194-200 (2011) (in Polish).
  • [13] Wojtkowski W., SEPIC converter for high power LED lighting, Przegląd Elektrotechniczny 86(10): 260-263 (2010). (in Polish).
  • [14] Chen Y., Dai W., Classification and Comparison of BPFC Techniques: A Review, Przegląd Elektrotechniczny 89(2a): 179-186 (2013) (in Polish).
  • [15] Kumar C., Kumar N., Radhika P., Torque ripple minimization in bldc motor using dcdc sepic converter, Przegląd Elektrotechniczny 90(9): 146-150 (2014) (in Polish).
  • [16] Styński S., Malinowski M., Sędłak M., Sobczuk D., Analysis and comparison of single-phase multilevel PWM flying capacitor converters, Przegląd Elektrotechniczny 89(4): 1-7 (2013) (in Polish).
  • [17] Stala R., Pirog S., Baszynski M., Mondzik A., Penczek A., Czekonski J., Gasiorek S., Results of Investigation of Multicell Converters With Balancing CircuitPart I, IEEE Transactions on Industrial Electronics 56: 2610-2619 (2009).
  • [18] Stala R., Pirog S., Mondzik A., Baszynski M., Penczek A., Czekonski J., S. Gasiorek, Results of Investigation of Multicell Converters With Balancing CircuitPart II, IEEE Transactions on Industrial Electronics 56: 2620-2628 (2009).
  • [19] Meynard T. A., Foch H., Thomas P., Courault J., Jakob R., Nahrstaedt M., Multicell Converters: Basics Concepts and Industry Applications. IEEE Trans. Ind. Electron 49: 955-964 (2002).
  • [20] Płatek T., Multilevel FLC converters for traction applications, Przegląd Elektrotechniczny 84(11): 50-56 (2008) (in Polish).
  • [21] Swierczyński D., Kaźmierkowski M., Styński S., Analysis of multilevel AC/DC/AC flying capacitor converter fed from single-phase grid, Przegląd Elektrotechniczny 87(1): 153-158 (2011) (in Polish).
  • [22] Wilkinson R. H., Meynard T. A., Mouton H. du Toit, Natural Balance of Multicell Converters: The Two-Cell Case, IEEE Transactions on Power Electronics 21: 1649-1657 (2006).
  • [23] McGrath B. P., Holmes D. G., Analytical Modeling of Voltage Balance Dynamics for a Flying Capacitors Multilevel Converter, IEEE Transactions on Power Electronics 23: 543-550 (2008).
  • [24] Lewicki A., DC-link voltage balancing in cascaded H-Bridge converters, Archives of Electrical Engineering 63(3): 439-455 (2014).
  • [25] Stala R., Methods of DC-link voltage natural balancing in the single-phase NPC inverter with two three-level legs, Przegląd Elektrotechniczny 90(6): 154-159 (2014) (in Polish).
  • [26] Stala R., Application of Balancing Circuit for DC-Link Voltages Balance in a Single-Phase Diode-Clamped Inverter With Two Three-Level Legs, IEEE Transactions on Industrial Electronics 58(9): 4185-4195 (2011).
  • [27] Stala R., A Natural DC-Link Voltage Balancing of Diode-Clamped Inverters in Parallel Systems, IEEE Transactions on Industrial Electronics 60(11): 5008-5018 (2013).
Uwagi
PL
Opracowanie ze środków MNiSW w ramach umowy 812/P-DUN/2016 na działalność upowszechniającą naukę.
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Bibliografia
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