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Test Procedures for Synchronized Oscillators Network CMOS VLSI Chip

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EN
Abstrakty
EN
The paper presents test procedures designed for application - specific integrated circuit (ASIC) CMOS VLSI chip prototype that implements a synchronized oscillator neural network with a matrix size of 32×32 for object detecting in binary images. Networks of synchronized oscillators are recently developed tool for image segmentation and analysis. This paper briefly introduces synchronized oscillators network. Basic chip analog building blocks with their test procedures and measurements results are presented. In order to do measurements, special basic building blocks test structures have been implemented in the chip. It let compare Spectre simulateions results to measurements results. Moreover, basic chip analog building blocks measurements give precious information about their imperfections caused by MOS transistor mismatch. This information is very usable during design and improvement of a special setup for chip functional tests. Improvement of the setup is a digitally assisted analog technique. It is an original idea of oscillators tuning procedure used during chip prototype testing. Such setup, oscillators tuning procedure and segmentation of sample binary images are presented.
Twórcy
autor
  • Institute of Electronics, Lodz University of Technology, Wolczanska 211/215, 90-924 Lodz, Poland
  • Institute of Electronics, Lodz University of Technology, Wolczanska 211/215, 90-924 Lodz, Poland
Bibliografia
  • [1] S. Suh, S. Itoh, S. Aoyama, S. Kawahito, “Column-parallel correlated multiple sampling circuits for CMOS image sensors and their noise reduction effects”, Sensors, 10, pp. 9139-9154, 2010.
  • [2] A. Zalewska, M. Strzelecki, P. Janowski.; E. Brzezińska-Błaszczyk, “Computer analysis of normal and basal cell carcinoma mast cells”, Med. Sci. Monitor, 7, pp. 260-265, 2001.
  • [3] D. Jirak, J. Kriz, M. Strzelecki; J. Yang, C. Hasilo; D. J. White, P. J. Foster, “Monitoring the survival of islet transplants by MRI using a novel technique for their automated detection and quantification”, Magn. Resonan. Mater. Phys. Biol. M., 22, pp. 257-265, 2009.
  • [4] J. Cosp,J. Madrenas, “Scene segmentation using neuromorphic oscillatory networks”, IEEE Trans. Neural Network, 14, pp. 1278-1296, 2003.
  • [5] D. Wang, D. Terman, “Locally excitatory globally inhibitory oscillators network”. IEEE Trans. Neural Network, 6, pp. 283-286, 1995.
  • [6] M. Strzelecki; J. Kowalski; H. Kim, S. Ko, “A new CNN oscillator model for parallel image segmentation”, Int. J. Bifurcation Chaos, 18, pp. 1999-2015, 2008.
  • [7] J. Kowalski , M. Strzelecki, H. Kim, “Implementation of a Synchronized Oscillator Circuit for Fast Sensing and Labeling of Image Objects”, Sensors, vol. 11, no. 4, pp. 3401-3417, 2011, doi:10.3390/s110403401.
  • [8] B. Murmann, "Digitally Assisted Analog Circuits – A Motivational Overview," ISSCC Special-Topic Evening Session (SE1.1), Feb. 2007.
  • [9] M. J. Pelgrom, A. C. J. Duinmaijer and A. P. G. Welbers, “Matching Properties of MOS Transistors”, IEEE Journal of Solid-State Circuits, vol.24, no.5, pp.1433-1439, October 1989.
  • [10] M. Conti, P. Crippa, S. Orcioni, and C. Turchetti, “Layout-Based Statistical Modeling for the Prediction of the Matching Properties of MOS transistors”, IEEE Transactions on Circuits and Systems - I: Fundamental Theory and Applications, vol. 49, no. 5, pp. 680-685, May 2002.
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Bibliografia
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bwmeta1.element.baztech-6b01f813-15d6-48a2-bdd0-53ce8323e475
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