Graphene-based Current Mode Logic Circuits : a Simulation Study for an Emerging Technology

• Autorzy: Abdollahi Hassan , Hooshmand Reza , Owlia Hadi

Identyfikatory

DOI

10.24425/ijet.2019.129789

• Języki publikacji: EN

Abstrakty

EN

In this paper, the usage of graphene transistors is introduced to be a suitable solution for extending low power designs. Static and current mode logic (CML) styles on both nanoscale graphene and silicon FINFET technologies are compared. Results show that power in CML styles approximately are independent of frequency and the graphene-based CML (G-CML) designs are more power-efficient as the frequency and complexity increase. Compared to silicon-based CML (Si-CML) standard cells, there is 94% reduction in power consumption for G-CML counterparts. Furthermore, a G-CML 4-bit adder respectively offers 8.9 and 1.7 times less power and delay than the Si-CML adder.

Słowa kluczowe

EN

current-mode logic; CML; graphene; graphene FET; low-power design

• Wydawca: Polish Academy of Sciences, Committee of Electronics and Telecommunication
• Czasopismo: International Journal of Electronics and Telecommunications
• Rocznik: 2019
• Tom: Vol. 65, No. 3
• Strony: 381--388
• Opis fizyczny: Bibliogr. 42 poz., wykr., rys., tab.

Twórcy

autor

Abdollahi Hassan

• Department of Electrical Engineering, Shahid Sattari Aeronautical University of Science and Technology, Tehran, Iran

autor

Hooshmand Reza

• Department of Electrical Engineering, Shahid Sattari Aeronautical University of Science and Technology, Tehran, Iran

autor

Owlia Hadi

• Department of Electrical Engineering, Faculty of Engineering, Ardakan University, P.O. Box 184, Ardakan, Iran

Bibliografia

• [1] J. M. Rabaey, M. Pedram, Low Power Design Methodologies. Springer Verlag, 2012.
• [2] M. Alioto, Enabling the Internet of Things From Integrated Circuits to Integrated Systems. Cham: Springer International Publishing, 2017.
• [3] D. Rossi, V. Tenentes, S. Yang, S. Khursheed, and B. M. Al-Hashimi, “Aging Benefits in Nanometer CMOS Designs,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 64, no. 3, pp. 324–328, 2017.
• [4] S. Kalra and A. B. Bhattacharyya, “Ultra Low Power Design for Digital CMOS Circuits Operating Near Threshold,” International Journal of Electronics and Telecommunications, vol. 63, no. 4, pp. 369–374, 2017.
• [5] M. Alioto, “Ultra-Low Power VLSI Circuit Design Demystified and Explained: A Tutorial,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 59, no. 1, pp. 3–29, 2012.
• [6] M. Sharma, R. Gautam, M.A. Khan, “Low Power VLSI Circuit Design using Energy Recovery Techniques,” in: V.K. Bhaaskaran, Design and Modeling of Low Power VLSI Systems, IGI Global, Delhi, 2016, pp. 128-164.
• [7] E. Panahifar and A. Hassanzadeh, “A Modified Signal Feed-Through Pulsed Flip- Flop for Low Power Applications,” International Journal of Electronics and Telecommunications, vol. 63, no. 3, pp. 241–246, 2017.
• [8] “International technology roadmap for semiconductors,” International technology roadmap for semiconductors. [Online]. Available: http://www.itrs.net. [Accessed: 1-Feb-2019].
• [9] H. Owlia, P. Keshavarzi, and A. Rezai, “A novel digital logic implementation approach on nanocrossbar arrays using memristor-based multiplexers,” Microelectronics Journal, vol. 45, no. 6, pp. 597–603, 2014.
• [10] S. Tabrizchi, A. Panahi, F. Sharifi, K. Navi, and N. Bagherzadeh, “Method for designing ternary adder cells based on CNFETs,” IET Circuits, Devices & Systems, vol. 11, no. 5, pp. 465–470, Jan. 2017.
• [11] S. Moysidis, I. G. Karafyllidis, and P. Dimitrakis, “Graphene Logic Gates,” IEEE Transactions on Nanotechnology, vol. 17, no. 4, pp. 852–859, 2018.
• [12] A. Bellaouar, Low-power digital vlsi design: circuits and systems. Place of publication not identified: Springer, 2012.
• [13] N. S. Kim, T. Austin, D. Blaauw, T. Mudge, K. Flautner, J. S. Hu, M. Irwin, M. Kandemir, and V. Narayanan, “Leakage current: Moores law meets static power,” Computer, vol. 36, no. 12, pp. 68–75, 2003.
• [14] S. Sato, “Graphene for nanoelectronics,” Japanese Journal of Applied Physics, vol. 54, no. 4, p.040102, 2015.
• [15] H. Owlia and P. Keshavarzi, “Investigation of the novel attributes of a double-gate graphene nanoribbon FET with AlN high-κ dielectrics,” Superlattices and Microstructures, vol. 75, pp. 613–620, 2014.
• [16] H. Owlia and P. Keshavarzi, “A bilayer graphene nanoribbon field-effect transistor with a dual-material gate,” Materials Science in Semiconductor Processing, vol. 39, pp. 636–640, 2015.
• [17] M. Saremi, M. Saremi, H. Niazi, and A. Y. Goharrizi, “Modeling of lightly doped drain and source graphene nanoribbon field effect transistors,” Superlattices and Microstructures, vol. 60, pp. 67–72, 2013.
• [18] L. Huang, H. Xu, Z. Zhang, C. Chen, J. Jiang, X. Ma, B. Chen, Z. Li, H. Zhong, and L.-M. Peng, “Graphene/Si CMOS Hybrid Hall Integrated Circuits,” Scientific Reports, vol. 4, no. 1, 2014.
• [19] M. Alioto and G. Palumbo, Model and design of bipolar and MOS current-mode logic: CML, ECL and SCL digital circuits. Dordrecht: Springer, 2005.
• [20] M. Alioto and G. Palumbo, “Feature - Power-aware design techniques for nanometer MOS current-mode logic gates: a design framework,” IEEE Circuits and Systems Magazine, vol. 6, no. 4, pp. 42–61, 2006.
• [21] O. Lozada and G. Espinosa, “An improved high speed, and low voltage CMOS current mode logic latch,” Analog Integrated Circuits and Signal Processing, vol. 90, no. 1, pp. 247–252, 2017.
• [22] Y. Bai, Y. Song, M. N. Bojnordi, A. Shapiro, E. G. Friedman, and E. Ipek, “Back to the Future: Current-Mode Processor in the Era of Deeply Scaled CMOS,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 4, pp. 1266–1279, 2016.
• [23] K. Bernstein, D. J. Frank, A. E. Gattiker, W. Haensch, B. L. Ji, S. R. Nassif, E. J. Nowak, D. J. Pearson, and N. J. Rohrer, “High-performance CMOS variability in the 65-nm regime and beyond,” IBM Journal of Research and Development, vol. 50, no. 4.5, pp. 433–449, 2006.
• [24] H. A. E. Hamid, B. Iñiguez, V. Kilchytska, D. Flandre, and Y. Ismail, “An analytical 3D model for short-channel effects in undoped FinFETs,” Journal of Computational Electronics, vol. 14, no. 2, pp. 500–505, 2015.
• [25] Y. S. Chauhan, S. Venugopalan, M.A. Karim, S. Khandelwal, N. Paydavosi, P. Thakur, A.M. Niknejad, C. C. Hu. “BSIM—Industry standard compact MOSFET models,” in Proc. Solid-State Device Research Conference (ESSDERC), Bordeaux, 2012, pp. 46-49.
• [26] S. Sinha, G. Yeric, V. Chandra, B. Cline, Y. Cao, “Exploring sub-20nm FinFET design with predictive technology models, in: ACM Proc. the 49th Annual Design Automation Conference,” 2012, pp. 283-288.
• [27] “Predictive Technology Model (PTM),” Predictive Technology Model (PTM). [Online]. Available: http://ptm.asu.edu/. [Accessed: 1-Feb-2019].
• [28] K. S. Novoselov, “Electric Field Effect in Atomically Thin Carbon Films,” Science, vol. 306, no. 5696, pp. 666–669, 2004.
• [29] A. K. Geim and K. S. Novoselov, “The rise of graphene,” Nature Materials, vol. 6, no. 3, pp. 183–191, 2007.
• [30] F. Schwierz, “Graphene transistors,” Nature Nanotechnology, vol. 5, no. 7, pp. 487–496, 2010.
• [31] Z. Yan, D. L. Nika, and A. A. Balandin, “Thermal properties of graphene and few-layer graphene: applications in electronics,” IET Circuits, Devices & Systems, vol. 9, no. 1, pp. 4–12, 2015.
• [32] F. T. L. E.F, S. Roche, and J.-C. Charlier, Introduction to graphene-based nanomaterials: from electronic structure to quantum transport. New York: Cambridge University Press, 2014.
• [33] Y.-W. Son, M. L. Cohen, and S. G. Louie, “Energy Gaps in Graphene Nanoribbons,” Physical Review Letters, vol. 97, no. 21, 2006.
• [34] Y. Yoon, G. Fiori, S. Hong, G. Iannaccone, and J. Guo, “Performance Comparison of Graphene Nanoribbon FETs With Schottky Contacts and Doped Reservoirs,” IEEE Transactions on Electron Devices, vol. 55, no. 9, pp. 2314–2323, 2008.
• [35] Y.-Y. Chen, A. Sangai, A. Rogachev, M. Gholipour, G. Iannaccone, G. Fiori, and D. Chen, “A SPICE-Compatible Model of MOS-Type Graphene Nano-Ribbon Field-Effect Transistors Enabling Gate- and Circuit-Level Delay and Power Analysis Under Process Variation,” IEEE Transactions on Nanotechnology, vol. 14, no. 6, pp. 1068–1082, 2015.
• [36] P. Michetti and G. Iannaccone, “Analytical Model of One-Dimensional Carbon-Based Schottky-Barrier Transistors,” IEEE Transactions on Electron Devices, vol. 57, no. 7, pp. 1616–1625, 2010.
• [37] M. Choudhury, Y. Yoon, J. Guo, K. Mohanram, “Technology exploration for graphene nanoribbon FETs,” in: ACM proceedings of the 45th annual Design Automation Conference, 2008, pp. 272-277.
• [38] S. Fregonese, C. Maneux, T. Zimmer, “A versatile compact model for ballistic 1D transistor: Applications to GNRFET and CNTFET,” in: IEEE international semiconductor device research symposium (ISDRS'09), 2009, pp. 1-2.
• [39] S. Datta, Quantum transport: atom to transistor. UK: Cambridge University Press, 2005.
• [40] H. Owlia and P. Keshavarzi, “Locally Defect-Engineered Graphene Nanoribbon Field-Effect Transistor,” IEEE Transactions on Electron Devices, vol. 63, no. 9, pp. 3769–3775, 2016.
• [41] H. Owlia, P. Keshavarzi, and M. B. Nasrollahnejad, “Effects of Stone-Wales Defect Position in Graphene Nanoribbon Field-Effect Transistor,” Journal of Nano- and Electronic Physics, vol. 9, no. 6, 2017.
• [42] S. Mangard, E. Oswald, and T. Popp, Power analysis attacks: revealing the secrets of smart cards. NY: Springer, 2008.