FPGA Implementation of Decision Trees and Tree Ensembles for Character Recognition in Vivado Hls

• Autorzy: Kułaga R. , Gorgoń M.
• Języki publikacji: EN

Abstrakty

EN

Decision trees and decision tree ensembles are popular machine learning methods, used for classification and regression. In this paper, an FPGA implementation of decision trees and tree ensembles for letter and digit recognition in Vivado High-Level Synthesis is presented. Two publicly available datasets were used at both training and testing stages. Different optimizations for tree code and tree node layout in memory are considered. Classification accuracy, throughput and resource usage for different training algorithms, tree depths and ensemble sizes are discussed. The correctness of the module’s operation was verified using C/RTL cosimulation and on a Zynq-7000 SoC device, using Xillybus IP core for data transfer between the processing system and the programmable logic.

Słowa kluczowe

EN

FPGA implementation; computer networks; training algorithms

• Wydawca: Instytut Telekomunikacji i Informatyki Uniwersytetu Technologiczno-Przyrodniczego w Bydgoszczy
• Czasopismo: Image Processing & Communications
• Rocznik: 2014
• Tom: Vol. 19, no. 2-3
• Strony: 71--82
• Opis fizyczny: Bibliogr. 17 poz., rys

Twórcy

autor

Kułaga R.

• AGH University of Science and Technology, Department of Automatics and Bioengineering Mickiewicza Ave., 30, 30-059 Kraków, Poland

autor

Gorgoń M.

• AGH University of Science and Technology, Department of Automatics and Bioengineering Mickiewicza Ave., 30, 30-059 Kraków, Poland

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