Some Schemes for Implementation of Arithmetic Operations with Complex Numbers Using Squaring Units

• Autorzy: Cariow A. , Cariowa G.
• Języki publikacji: EN

Abstrakty

EN

In this paper, new schemes for a squarer, multiplier and divider of complex numbers are proposed. Traditional structural solutions for each of these operations require the presence of some number of general-purpose binary multipliers. The advantage of our solutions is a removing of multiplications through replacing them by less costly squarers. We use Logan's trick and quarter square technique, which propose to replace the calculation of the product of two real numbers by summing the squares. Replacing usual multipliers with digital squares implies the reducing power consumption as well as decreases the complexity of the hardware circuit. The squarer requiring less area and power as compared to general-purpose multiplier, it is interesting to assess the use of squarers to implementation of complex arithmetic.

Słowa kluczowe

EN

complex number arithmetic; squaring unit; implementation complexity reduction; hardware implementation

• Wydawca: Wydawnictwo PAK
• Czasopismo: Measurement Automation Monitoring
• Rocznik: 2017
• Tom: Vol. 63, No. 6
• Strony: 209--211
• Opis fizyczny: Bibliogr. 11 poz., rys., tab., wzory

Twórcy

autor

Cariow A.

• West Pomieranian University of Technology, Szczecin 49 Żołnierska St., 71-210, Szczecin, Poland

autor

Cariowa G.

• West Pomieranian University of Technology, Szczecin 49 Żołnierska St., 71-210, Szczecin, Poland

Bibliografia

• [1] Nikolova Z., Iliev G., Ovtcharov M. and Poulkov V.: Complex Digital Signal Processing in Telecommunications. In “Applications of Digital Signal Processing” Edited by Christian Cuadrado-Laborde, InTech Open Access Publisher, 2011, pp. 3-24.
• [2] Brown J. A., Crowder H.: Graphics Application Using Complex Numbers in APL2 Technical Report: TR 03.265, Santa Teresa Laboratory San Jose, CA. March 1985
• [3] Martin, K.: Complex signal processing is not – complex. Proc. of the 29th European Conf. on Solid-State Circuits (ESSCIRC'03), 2003, pp. 3-14, Estoril, Portugal, 16-18 Sept. 2003.
• [4] Cariow A., Cariowa G.: An algorithm for complex-valued vector-matrix multiplication. Electrical Review, 2012, R88, No. 10b, pp. 213-216.
• [5] Deshpande A., Draper J.: Squaring units and a comparison with multipliers. In 53rd IEEE International Midwest Symp. on Circuits and Systems (MWSCAS 2010), Seattle, Washington August 1st-4th, 2010, pp. 1266–1269, doi: 10.1109/MWSCAS.2010.5548763.
• [6] Liddicoat A. A., Flynn M. J.: Parallel Computation of the Square and Cube Function. Computer Systems Laboratory; Stanford University, Technical report No. CSL-TR-00-808, August 2000.
• [7] Knuth D.E.: The Art Of Computing Programming, Volume 2, Seminumerical Algorithms, Addison-Wesley, Reading, MA, USA, Second Ed., 1981.
• [8] Logan J. R.: A square-summing high-speed multiplier. Comput. Des., 1971, pp. 67-70.
• [9] Johnson E. L.: A Digital Quarter Square Multiplier. IEEE Transactions on Computers, vol. C-29, no. 3, pp. 258–261, 1980, doi:10.1109/TC.1980.1675558.
• [10] Granata J., Conner M., Tolimieri R.: The Tensor product: A mathematical programming language for FFTs and other fast DSP operations. IEEE Signal Processing Magazine, 1992. No. 1, pp. 41-48.
• [11] Cariow A.: Strategies for the Synthesis of Fast Algorithms for the Computation of the Matrix-vector Products. Journal of Signal Processing Theory and Applications, 2014, vol. 3, No. 1, pp. 1-19.

Uwagi

PL

Opracowanie ze środków MNiSW w ramach umowy 812/P-DUN/2016 na działalność upowszechniającą naukę (zadania 2017).