New ternary decoders using hybrid memristor-MOS logic

• Autorzy: Kumar Ramesh , Nagar Bal Chand

Identyfikatory

DOI

10.24425/ijet.2025.153596

• Języki publikacji: EN

Abstrakty

EN

Integrating memristor technology with traditional CMOS has led to innovative designs for ternary logic, significantly enhancing the performance and efficiency of digital integrated circuits. This hybrid approach takes advantage of the unique properties of memristors, including low power consumption, compact size, and non-volatility, to develop ternary logic circuits that outperform conventional binary systems in terms of area and energy efficiency. This article presents two new low-power ternary decoders designed using a hybrid memristor-MOS logic approach. The decoders were simulated and analyzed using SPICE, and their performance was compared with existing circuits. The results indicate that the power-efficient decoder uses 44.44% fewer transistors and dissipates 97.78% less power than previously documented circuits.

Słowa kluczowe

EN

Ternary logic; Memristor; Ternary Decoder; MVL; MOS

• Wydawca: Polish Academy of Sciences, Committee of Electronics and Telecommunication
• Czasopismo: International Journal of Electronics and Telecommunications
• Rocznik: 2025
• Tom: Vol. 71, No. 2
• Strony: 489--494
• Opis fizyczny: Bibliogr. 26 poz., rys., tab.

Twórcy

autor

Kumar Ramesh

• National Institute of Technology (NIT), Patna, India

autor

Nagar Bal Chand

• National Institute of Technology (NIT) , Patna, India

Bibliografia

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Uwagi

Opracowanie rekordu ze środków MNiSW, umowa nr POPUL/SP/0154/2024/02 w ramach programu "Społeczna odpowiedzialność nauki II" - moduł: Popularyzacja nauki (2025).