A Hardware-Efficient Structure of Complex Numbers Divider

• Autorzy: Cariow A. , Cariowa G.
• Języki publikacji: EN

Abstrakty

EN

In this correspondence an efficient approach to structure of hardware accelerator for calculating the quotient of two complex-numbers with reduced number of underlying binary multipliers is presented. The fully parallel implementation of a complex-number division using the conventional approach to structure organization requires 4 multipliers, 3 adders, 2 squarers and 2 divider while the proposed structure requires only 3 multipliers, 6 adders, 2 squarers and 2 divider. Because the hardware complexity of a binary multiplier grows quadratically with operand size, and the hardware complexity of an binary adder increases linearly with operand size, then the complex-number divider structure containing as little as possible embedded multipliers is preferable.

Słowa kluczowe

EN

complex-number divider; hardware complexity reduction; VLSI implementation

• Wydawca: Wydawnictwo PAK
• Czasopismo: Measurement Automation Monitoring
• Rocznik: 2017
• Tom: Vol. 63, No. 6
• Strony: 212--213
• Opis fizyczny: Bibliogr. 11 poz., rys., wzory

Twórcy

autor

Cariow A.

• West Pomieranian University Of Technology, Szczecin, 49 Żołnierska St., 71-210, Szczecin, Poland

autor

Cariowa G.

• West Pomieranian University Of Technology, Szczecin, 49 Żołnierska St., 71-210, Szczecin, Poland

Bibliografia

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• [3] Nikolova Z., Iliev G., Ovtcharov M. and Poulkov V.: Complex Digital Signal Processing in Telecommunications. In: Applications of Digital Signal Processing, edited by Christian Cuadrado-Laborde. InTech Open Access Publisher, 2011, pp. 3-24.
• [4] Cariow A., Cariowa G.: A rationalized algorithm for complex-valued inner product calculation. Pomiary Automatyka Kontrola, 2012, 58, 674-676.
• [5] Stewart G. W.: A note on complex division. ACM Transactions on Mathematical Software, 1985, vol. 11, no. 3, pp. 238–324, doi:10.1145/214408.214414.
• [6] Varghese A. A. Pradeep, C., Eapen, M. E., Radhakrishnan, R.: FPGA Implementation of Area-Efficient IEEE 754 Complex Divider, International Conference on Emerging Trends in Engineering, Science and Technology (ICETEST - 2015): Procedia Technology, vol. 24, 2016, pp. 1120–1126, doi:10.1016/j.protcy.2016.05.245.
• [7] López-Martínez, F. J., del Castillo-Sánchez, E, Entrambasaguas J. T., Martos-Naya E.: Iterative-Gradient Based Complex Divider FPGA Core with Dynamic Configurability of Accuracy and Throughput. Journal of Signal Processing Systems, 2011, vol. 62, no. 3, pp. 319-324, doi 10.1007/s11265-010-0464-y.
• [8] Knuth D. E.: The Art Of Computing Programming. Volume 2, Seminumerical Algorithms, Addison-Wesley, Reading, MA, USA, Second Ed., 1981.
• [9] Blahut R. E.: Fast algorithms for digital signal processing. Addison-Wesley Publishing company, Inc. 1985.
• [10] Cariow A.:An algorithm for dividing two complex numbers. CoRR abs/1608.07596 2016, pp. 1-4.
• [11] Cariow A.: Strategies for the Synthesis of Fast Algorithms for the Computation of the Matrix-vector Products, Journal of Signal Processing Theory and Applications, 2014, vol. 3, No. 1, pp. 1-19. doi:10.7726/jspta.20141001.

Uwagi

PL

Opracowanie ze środków MNiSW w ramach umowy 812/P-DUN/2016 na działalność upowszechniającą naukę (zadania 2017).