High-resolution time-interval generator

• Autorzy: Chaberski D.

Identyfikatory

DOI

10.15199/48.2017.10.06

Warianty tytułu

PL

Wysokorozdzielczy generator odcinków czasu

• Języki publikacji: EN

Abstrakty

EN

The paper presents the design of a high-resolution TI (Time-Interval) generator implemented into FPGA (Field-Programmable-Gate-Array) Xilinx Virtex 5 device and obtained experimental test results. The improvement of resolution is realized by the use of a chain of DCDEs (Digitally- Controlled-Delay-Elements). The presented TI generator allows for generating either TIs of constant length or TIs of specified Gaussian distribution. Experimental results include TI histograms measured by the LeCroy 804Zi oscilloscope.

PL

Artykuł przedstawia projekt wysokorozdzielczego generatora odcinków czasu zaimplementowanego w strukturze programowalnej FPGA Xilinx Virtex 5 wraz z wynikami eksperymentalnymi uzyskanymi z wykorzystaniem oscyloskopu LeCroy 804Zi. Wzrost rozdzielczości jest możliwy dzięki stosowaniu łańcucha zbudowanego z elementów opóźniających sterowanych cyfrowo. Prezentowany generator pozwala na generowanie odcinków czasu o określonych przez użytkownika parametrach rozkładu Gausa.

Słowa kluczowe

EN

FPGA; time interval; time stamps; tapped-delay-line

PL

FPGA; odcinek czasu; stempel czasu; wielosegmentowa linia opóźniająca

• Wydawca: Wydawnictwo SIGMA-NOT
• Czasopismo: Przegląd Elektrotechniczny
• Rocznik: 2017
• Tom: R. 93, nr 10
• Strony: 25--32
• Opis fizyczny: Bibliogr. 21 poz., rys.

Twórcy

autor

Chaberski D.

• Nicolaus Copernicus University, Faculty of Physics, Astronomy and Informatics, 87-100 Toruń, Poland

Bibliografia

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• [8] Chen P., Chen P.-Y., Lai J.-S., Chen Y.-J., FPGA Vernier Digital-to-Time Converter With 1.58 ps Resolution and 59.3 Minutes Operation Range, IEEE Trans. Circuits Syst. I, Reg. Papers, 57 (2010), n. 6, 1134-1142
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• [10] Tang Wenjia, Kim Hongjoon, Compact, tunable large group delay line, Wireless and Microwave Technology Conference, WAMICON '09. IEEE 10th Annual, Florida, 2009, 1-3
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• [12] Kim Choul-Young, Yang Jaemo, Kim Dong-Wook, Hong Songcheol, A K-Band CMOS Voltage Controlled Delay Line Based on an Artificial Left-Handed Transmission Line, IEEE Microwave and Wireless Components Letters, 18 (2008), n. 18, 731-733
• [13] Wu J., Uneven Bin Width Digitization and a Timing Calibration Method Using Cascaded PLL, FERMILAB-CONF-14-140-E
• [14] Zieliński M., Chaberski D., Kowalski M., Frankowski R., Grzelak S., High-resolution time-interval measuring system implemented in single FPGA device, Measurement, 35 (2004), n. 3, 311-317
• [15] Kalisz J., Review of methods for time interval measurements with picosecond resolution, Metrologia, 41 (2004), n. 1, 17-32
• [16] Chaberski D., Time-to-digital-converter based on multipletapped-delay-line, Measurement, 89 (2016), 87-96
• [17] Giordano R., Ameli F., Bifulco P., Bocci V., Cadeddu S., Izzo V., Lai A., Mastroianni S., Aloisio. A., High-Resolution Synthesizable Digitally-Controlled Delay Lines, IEEE Transactions on Nuclear Science, 62 (2015), n. 6, 3163-3171
• [18] Szplet R., Sondej D., Grzęda G., High-Precision Time Digitizer Based on Multiedge Coding in Independent Coding Lines, IEEE Transactions on Instrumentation and Measurement, 65 (2016), n. 8, 1884-1894
• [19] Szplet R., Kwiatkowski P., Jachna Z., Różyc K., An Eight-Channel 4.5-ps Precision Timestamps-Based Time Interval Counter in FPGA Chip, IEEE Transactions on Instrumentation and Measurement, 65 (2016), n. 9, 2088-2100
• [20] Li J., Zheng Z., Liu M., Wu S., Large Dynamic Range Accurate Digitally Programmable Delay Line with 250-ps Resolution, International Conference on Signal Processing, Beijing, China, 16-20 Nov. 2006
• [21] Chaberski D., Zieliński M., Grzelak S., The new method of calculation sum and difference histogram for quantized data, Measurement, 42 (2009), 1388-1394

Uwagi

Opracowanie ze środków MNiSW w ramach umowy 812/P-DUN/2016 na działalność upowszechniającą naukę (zadania 2017).