PL EN


Preferencje help
Widoczny [Schowaj] Abstrakt
Liczba wyników
Tytuł artykułu

Power-saving voltage-to-current conversion with the use of CMOS differential amplifier

Autorzy
Treść / Zawartość
Identyfikatory
Warianty tytułu
Języki publikacji
EN
Abstrakty
EN
Differential amplifiers are well known as input stage preamplifiers. This is because they exhibit the ability to reduce unwanted common-mode effects considerably. As a consequence, both noise and input signal of the amplifier can have low values. Proper operation of differential amplifiers is possible when implemented in chip form. For typical use of such CMOS amplifiers, input signals are delivered to differential-pair gate-terminals while tail terminal is used to ensure the required bias of the pair. The paper shows that the roles of gates and tail terminal can be changed. In other words, the tail current can be used as input signal while the gate ones as voltages controlling the amplifier gain. This enables to combine the achievable low noise with power efficient operation of the circuit. Necessary conditions for that are discussed in this paper. Suitability of atypically used differential amplifiers for voltage-to-current conversion is explained. Two examples of CMOS circuits implementing power economic conversion of this type are presented.
Twórcy
autor
  • Faculty of Telecommunication, Computer Science & Electrical Engineering, University of Technology and Life Sciences, Bydgoszcz, Poland
Bibliografia
  • [1] G. Cauwenberghs, M. A. Bayoumi, E. Sanchez-Sinencio, “Learning on silicon: Adaptive VLSI Neural Systems”, Kluwer Academic Publishers, 1999.
  • [2] S. Fakhraie, K. C. Smith, “VLSI-compatible implementations for artificial neural networks”, Kluwer Academic Publishers, 1997
  • [3] B. Linares-Barranco, E. Sanchez-Sinencio, A. Rodriguez-Vazquez, J. L. Huertas, “A CMOS Analog Adaptive BAM with On-Chip Learning and Weight Refreshing”, IEEE Transactions on Neural Networks, Vol. 4, No. 3, 1993, pp.445-455. 1993
  • [4] Shih-Lun Chen; Ho-Yin Lee; Yu-Wen Chu; Chiung-An Chen; Chin- Chun Lin; Ching-Hsing Luo, “A variable control system for wireless body sensor network”, IEEE International Symposium on Circuits and Systems (ISCAS), 18-21, pp.2034-2037, May 2008.
  • [5] Rodriques Vazques, S. Espejo, R. Domingues-Castro, J. L. Huertas and Sanches-Sinencio, “Current-mode techniques for the implementation of continuous and discrete-time cellular neural networks”, IEEE Transactions on CAS , CAS-40, pp. 132-146, 1993.
  • [6] R. Wojtyna, M. Kalista, „Quasi-linear low-power variable-gain transconductor for VLSI CMOS artificial neural networks”, Int. Workshop MIXDES’2000, pp. 473-476, Gdynia 2000.
  • [7] W. Machowski, S. Kuta, J. Jasielski, J. Kołodziejski, „Fast low voltage analog fourquadrant multipliers based on CMOS inverters”, International Journal of Electronics and Telecommunications, vol. 56, no. 4, s. 381-386, 2010.
  • [8] R. Wojtyna, T. Talaśka, „Improved Power-Saving Synapse for Adaptive Neuroprocessing on Silicon”, ICSES’2004, pp. 27-30, 2004.
  • [9] R. Wojtyna, „Analog-technique-based neuroprocessing implemented in hardware”, IEEE Workshop SPA 2009 (Signal Processing – Algorithms, Architectures, Arrangements and Applications), pp. 9-12, 2009.
  • [10] R. Długosz, T. Talaśka, W. Pedrycz, R. Wojtyna, “Realization of the Conscience Mechanism in CMOS Implementation of Winner-Takes-All Self-Organizing Neural Networks”, IEEE Trans. Neural Networks, Vol. 21, No. 6, pp.961-971, 2010.
  • [11] R. Długosz, T. Talaśka, “Low Power Current-Mode Binary-Tree Asynchronous Min/Max Circuit”, Microelectronics Journal, Elsevier, No.1, pp.64–73, January 2010.
  • [12] R. Wojtyna, “CMOS transconductance-mode analog circuit for fast determining Euclidean distance”, Elektronika, Nr 4/2007, pp. 65-68
  • [13] R. Wojtyna, “Analog low-voltage low-power CMOS circuit for learning Kohonen networks on silicon”, International Conference MIXDES’2010, pp. 209-214, 2010.
  • [14] R. Wojtyna, “Differential-pair-based Current-mode Analog Signal Processing”, International Conference MIXDES’2015, pp. 585-588 , Toruń 2015.
Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-623799fa-7d40-4e56-8d7b-6ebbf67593f2
JavaScript jest wyłączony w Twojej przeglądarce internetowej. Włącz go, a następnie odśwież stronę, aby móc w pełni z niej korzystać.