Characterizing the Inter-Thread Interference of Multi-Core Architectures for Accurate WCET Estimations of Real-Time Applications

• Autorzy: Chen F. , Zhang D. , Wang Z.

Warianty tytułu

PL

Charakterystyka interferencji przy architekturze wielordzeniowej do dokładnego określania parametru WCET w czasie rzeczywistym

• Języki publikacji: EN

Abstrakty

EN

Worst-Case Execution Time (WCET) estimation of an application in a real-time system becomes more difficult due to inter-thread interference in shared resources multi-core architectures. This paper proposes an iterative approach to analyze cache interference based on circular dependencies between inter-thread interference and instruction fetch time. Our experiments indicate that the proposed approach can reasonably estimate inter-thread interference in shared caches and improve the tightness of WCET estimation by an average of 17.5%.

PL

W artykule zaproponowano iteracyjną metodę do analizy ukrytych interferencji bazującą na cyrkularnych zależnościach między wątkiem interferencji i czasie dostarczania instrukcji.

Słowa kluczowe

EN

inter-thread interference; multicore architecture; shared cache; WCET

PL

WCET; czas realizacji; interferencja

• Wydawca: Wydawnictwo SIGMA-NOT
• Czasopismo: Przegląd Elektrotechniczny
• Rocznik: 2012
• Tom: R. 88, nr 7b
• Strony: 332--335
• Opis fizyczny: Bibliogr. 10 poz., schem., tab.

Twórcy

autor

Chen F.

• School of Computer Science and Technology, National University of Defense Technology , China

autor

Zhang D.

• School of Computer Science and Technology, National University of Defense Technology , China

autor

Wang Z.

• School of Computer Science and Technology, National University of Defense Technology , China

Bibliografia

• [1] J. Anderson, J. Calandrino, and U. Devi. Real-time scheduling on multicore platforms. RTAS, 2006.
• [2] B. K. Bershad, B. J. Chen, D. Lee, and T. H. Romer. Avoiding conflict misses dynamically in large direct mapped caches. In ASPLOS, 1994.
• [3] Nan Guan, Martin Stigge, Wang Yi and Ge Yu. Cache-Aware Scheduling and Analysis for Multicores. In EMSOFT, 2009.
• [4] J. Yan and W. Zhang. WCET analysis for multi-core processors with shared L2 instruction caches. In Proc. of the 14th IEEE Real-Time and Embedded Technology and Applications Symposium, April 2008.
• [5] F.Y. Chen, D.S. Zhang and Z.Y. Wang. Static Analysis of Run-Time Inter-Core Interferences for Consecutive or Inconsecutive Concurrent Programs in Shared Cache Multicore Architectures. In Proc. of the 3rd International Conference on Computer Design and Applications (ICCDA 2011), May 2011.
• [6] F.Y. Chen, D.S. Zhang and Z.Y. Wang. Static Analysis of Run-Time Inter-Thread Interferences in Shared Cache Multi-Core Architectures based on Instruction Fetching Timing. In Proc. Of the IEEE International Conference on Computer Science and Automation Engineering (CSAE 2011), June 2011.
• [7] Li Xianfeng, Microarchitecture Modeling for Timing Analysis of Embedded Software. Dissertation for the Degree of Doctor of Philosophy in Computer science, National University of Singapore, 2005.
• [8] S. Chattopadhyay, A. Roychoudhury, and T. Mitra. Modeling shared cache and bus in multi-cores for timing analysis. In SCOPES, 2010.
• [9] X. Li, Y. Liang, T. Mitra and A. Roychoudhury. Chronos: a timing analyzer for embedded software. http://www.comp.nus.edu.sg/rpembed/chronos, October 2007.
• [10] Homepage of SNU real-time benchmark suite. http://archi.snu.ac.kr/realtime/benchmark/, Oct 2007.