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Estimation and correction of gain mismatch and timing error in time-interleaved ADCs based on DFT

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Warianty tytułu
Języki publikacji
EN
Abstrakty
EN
Time-interleaved analog-to-digital converter (ADC) architecture is crucial to increase the maximum sample rate. However, offset mismatch, gain mismatch, and timing error between time-interleaved channels degrade the performance of time-interleaved ADCs. This paper focuses on the gain mismatch and timing error. Techniques based on Discrete Fourier Transform (DFT) for estimating and correcting gain mismatch and timing error in an M-channel ADC are depicted. Numerical simulations are used to verify the proposed estimation and correction algorithm.
Rocznik
Strony
535--544
Opis fizyczny
Bibliogr. 19 poz., rys., wykr., wzory
Twórcy
autor
  • School of Automation Engineering, University of Electronic Science and Technology of China, Chengdu, China
autor
  • School of Automation Engineering, University of Electronic Science and Technology of China, Chengdu, China
autor
  • School of Automation Engineering, University of Electronic Science and Technology of China, Chengdu, China
Bibliografia
  • [1] Black, W.C., Jr., Hodges, D. (1980). Time interleaved converter arrays. IEEE J. Solid-State Circ., 15, 1022-1029.
  • [2] Elbornsson, J., Folkesson, K., Eklund, J.-E. (2002). Measurement verification of estimation method for time errors in a time-interleaved A/D converter system. In IEEEISCAS 2002, 3, 129-132.
  • [3] Chi Ho L., Hurst, P.J., Lewis, S.H. (2010). A four-channel time-interleaved ADC with digital calibration of interchannel timing and memory errors. IEEE J. Solid-State Circ., 45, 2091-2103.
  • [4] Kurosawa, N., Kobayashi, H., Maruyama, K., Sugawara, H., Kobayashi, K. (2001). Explicit analysis of channel mismatch effects in time-interleaved ADC systems. IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., 48, 261-271.
  • [5] Huawen, J., Lee, E.K.F. (2000). A digital-background calibration technique for minimizing timing-error effects in time-interleaved ADCs. IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., 47, 603-613.
  • [6] Jenq, Y.-C. (1990). Digital spectra of nonuniformly sampled signals: a robust sampling time offset estimation algorithm for ultra high-speed waveform digitizers using interleaving. IEEE Trans. Instrum. Meas., 39, 71-75.
  • [7] Fu, D., Dyer, K.C., Lewis, S.H., Hurst, P.J. (1998). A digital background calibration technique for time-interleaved analog-to-digital converters. IEEE J. Solid-State Circ., 33, 1904-1911.
  • [8] Munkyo, S., Rodwell, M.J.W., Madhow, U. (2005). Comprehensive digital correction of mismatch errors for a 400-msamples/s 80-dB SFDR time-interleaved analog-to-digital converter. IEEE Trans. Microw. Theory. Tech., 53, 1072-1082.
  • [9] Jamal, S.M., Fu, D., Singh, M.P., Hurst, P.J., Lewis, S.H. (2004). Calibration of sample-time error in a two-channel time-interleaved analog-to-digital converter. IEEE Trans. Circuits Syst. I, Regular Papers, 51, 130-139.
  • [10] Elbornsson, J., Eklund, J.-E. (2001). Blind estimation of timing errors in interleaved AD converters. In IEEEICASSP 2001, 6, 3913-3916.
  • [11] Huang, S., Levy, B.C. (2007). Blind calibration of timing offsets for four-Channel time-Interleaved ADCs. IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., 54, 863-876.
  • [12] Dyer, K.C., Fu, D., Lewis, S.H., Hurst, P.J. (1998). An analog background calibration technique for time-interleaved analog-to-digital converters. IEEE J. Solid-State Circ., 33, 1912-1919.
  • [13] Cheng-Chung, H., Fong-Ching, H., Chih-Yung, S., Chen-Chih, H., Ying-Hsi, L., Lee, C.-C., Razavi, B. (2007). An 11b 800MS/s time-interleaved ADC with digital background calibration. In IEEE ISSCC 2007, 464-615.
  • [14] Jamal, S.M., Fu, D., Chang, N.C.-J., Hurst, P.J., Lewis, S.H. (2002). A 10-b 120-Msample/s time-interleaved analog-to-digital converter with digital background calibration. IEEE J. Solid-State Circ., 37, 1618-1627.
  • [15] Gupta, S.K., Inerfield, M.A., Jingbo, W. (2006). A 1-GS/s 11-bit ADC with 55-dB SNDR, 250-mW power realized by a high bandwidth scalable time-interleaved architecture. IEEE J. Solid-State Circ.,41, 2650-2657.
  • [16] Pan, H., Tian, S., Ye, P. (2010). An adaptive synthesis calibration method for time-interleaved sampling systems. Metrol. Meas. Syst., 17(3), 405-414.
  • [17] Lai, L.S., Lee, S.W., Chuah, T.C. (2011). Phase extraction based efficient timing mismatch identification in time-interleaved analogue-to-digital converter systems. Electronics Letter, 47, 247-249.
  • [18] Pereira, J.M.D., Girao, P.M.B.S., Serra, A.M.C. (2004). An FFT-based method to evaluate and compensate gain and offset errors of interleaved ADC systems. IEEE Trans. Instrum. Meas., 53, 423-430.
  • [19] Vogel, C., Krall, C. (2008). Compensation of distortions caused by periodic nonuniform holding signals. In CNSDSP 2008, 152-155.
Uwagi
EN
This work was supported by the National Natural Science Foundation of China (No.61301263), the Specialized Research Fund for the Doctoral Program of Higher Educatio nof China (No.20120185130002), and the Fundamental Research Fund for the Central University of China (A03007023801217) and (A03008023801080).
Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-5ddac4c0-721c-4664-8ff2-36045d8ce22e
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