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Tytuł artykułu

The temperature dependence of subthreshold characteristics of Si and SiC power MOSFETs

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Warianty tytułu
Języki publikacji
EN
Abstrakty
EN
In the paper, subthreshold characteristics of Si and SiC MOSFET power transistors in a wide range of current and temperature are considered. Representative examples of measured iD-vGS dependencies for temperatures from 20°C up to over 140°C are presented and discussed. Substantial differences of the shapes obtained for Si and SiC devices are observed. The subthreshold slope and subthreshold swing coefficient are extracted from measured curves for two types of devices and compared.
PL
W niniejszym artykule porównano charakterystyki w obszarze podprogowym tranzystorów mocy MOSFET z krzemu i węglika krzemu w szerokim zakresie prądu i temperatury. Dla reprezentatywnej partii tranzystorów przedstawiono i omówiono pomiary zależności iD-vGS w szerokim zakresie temperatur od 20°C do ponad 140°C. Dodatkowo zaprezentowano różnice w wartości nachylenia oraz wahania współczynnika w obszarze podprogowym od temperatury otoczenia dla badanych tranzystorów z Si i SiC.
Rocznik
Tom
Strony
51--58
Opis fizyczny
Bibliogr. 12 poz., tab., wykr.
Twórcy
  • Faculty of Electronics and Computer Sciences, Koszalin University of Technology, Poland
autor
  • Faculty of Electronics and Computer Sciences, Koszalin University of Technology, Poland
Bibliografia
  • 1. E. Boufouss, L.A. Francis, P. Gerard, M. Assaad and D. Flandre, Ultra low power CMOS circuits working in subthreshold regime for high temperature and radiation environments, IMAPS, July 18-20, 2011, pp. 243-250.
  • 2. R. H. Iacob, A. Manolescu, Current-Mode References Based on MOS Subthreshold operation, U.P.B. Sci. Bull., Series C,Vol. 71, Iss.3, 2009, pp. 243-250.
  • 3. Y. Liu, R.P. Dick, Li Shang, H. Yang, Accurate Temperature-Dependent Integrated Circuit Leakage Power Estimation Is Easy, EDAA, 2007.
  • 4. L. Magnelli, F. Crupi, P. Corsonello, A 2.6nW, 0.45V Temperature-Compensated Subthreshold CMOS Voltage Reference, IEEE Journal of Solid-State Circuits, Vol. 46, No.2, February 2011, pp. 465-474.
  • 5. V. Sharma, S. Kumar, Design of Low-Power CMOS Cell Structures Using Subthreshold Conduction Region, Int. Journal of Scientific & Engineering Research, Vol. 2, Issue 2, Feb. 2011.
  • 6. Y. Taur, T.H. Ning, Fundamentals of Modern VLSI Devices, Cambridge University Press, 1998, Ch. 3.1.3.
  • 7. K. Roy, S. Mukhopadhyay and H. Mahmoodi-Meimand, Leakage Current Mechanisms and Leakage Reduction Techniques in Deep-Submicrometer CMOS Circuits, Proc. IEEE, Vol. 91, No. 2, Feb. 2003, pp. 305-327.
  • 8. R. Singh et al., Analysis of the Effect of Temperature Variations on Subthreshold Leakage Current in P3 and P4 SRAM Cells at Deep Sub-micron CMOS Technology, Int. Journal of Computer Applications, Vol. 35, No. 5, Dec. 2011, pp. 8-12.
  • 9. Y. Zeng, A. Softic and M.H. White, Characterization of Interface Traps in the Subthreshold Region of Implanted 4H and 6H-SiC MOSFET’s, Solid State Electronics, Vol. 46 (2002), pp. 1579-1582.
  • 10. A. Appaswamy, P. Chakraborty and J.D. Cressler, Influence of Interface Traps on the Temperature Sensitivity of MOSFET Drain Current Variations, IEEE Electron Device Letters, vol. 31, No. 5, (2010), pp. 387-369.
  • 11. S. Potbhare et al., Time Dependent Trapping and Generation-Recombination of Interface Charges: Modeling and Characterization for SiC MOSFET’s, Materials Science Forum, vol. 556-557, Sept. 2007, pp. 847-850.
  • 12. S. DasGupta et al., Extraction of Trapped Charge in 4H-SiC Metal Oxide Semiconductor Field Effect Transistors from Subthreshold Characteristics, Applied Physics Letters, vol. 99, No. 2, (2011), p. 23503.
Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-5d62df77-8527-4018-86df-ba4a5dfb5827
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