Spice simulation of substrate potential shift in HVCMOS technologies

• Autorzy: Stefanucci C. , Buccella P. , Kayal M. , Sallese J.-M.
• Języki publikacji: EN

Abstrakty

EN

High voltage CMOS active devices inherently include a parasitic vertical PNP bipolar transistor. When activated it injects holes into the substrate causing a dangerous potential shift. In this work a spice-modeling approach based on transistor layout is presented to simulate substrate de-biasing in Smart Power ICs. The proposed model relies on a parasitic substrate network without the need of a parasitic BJT in HVCMOS compact models. The results are compared with TCAD simulations at different temperatures showing good agreement. Potential shift of the substrate is analysed for different geometrical configurations to estimate the effect of P+ grounding schemes and backside contact.

Słowa kluczowe

EN

smart power ICs; HVCMOS modeling; vertical bipolar transistor; substrate potential shift

PL

smart power; modelowanie HVCMOS; pionowy tranzystor bipolarny

• Wydawca: Lodz University of Technology. Department of Microelectronics and Computer Science
• Czasopismo: International Journal of Microelectronics and Computer Science
• Rocznik: 2015
• Tom: Vol. 6, nr 4
• Strony: 142--147
• Opis fizyczny: Bibliogr. 18 poz., il. kolor., wykr.

Twórcy

autor

Stefanucci C.

• Swiss Federal Institute of Technology (EPFL), Lausanne, Switzerland

autor

Buccella P.

• Swiss Federal Institute of Technology (EPFL), Lausanne, Switzerland

autor

Kayal M.

• Swiss Federal Institute of Technology (EPFL), Lausanne, Switzerland

autor

Sallese J.-M.

• Swiss Federal Institute of Technology (EPFL), Lausanne, Switzerland

Bibliografia

• [1] M. Schrems, M. Knaipp, H. Enichlmair, V. Vescoli, R. Minixhofer, E. Seebacher, F. Leisenberger, E. Wachmann, G. Schatzberger, H. Gensin, “Scalable High Voltage CMOS technology for Smart Power and sensor applications”, Elektrotechnik and Informationstechnik, 125, 4, 2008.
• [2] S. F. Frere, P. Moens, B. Desoete, D. Wojciechowski, A. J. Walton, “An improved LDMOS transistor model that accurately predicts capacitance for all bias conditions”, Proc. ICMTS, pp. 75–79, 2005.
• [3] A. Bazigos, F. Krummenacher, J.M. Sallese, M. Bucher, E. Seebacher, W. Posch, K. Molnar, T. Mingchun, “A Physics-Based Analytical Compact Model for the Drift Region of the HV-MOSFET”, IEEE Trans. Electron Devices, vol.58, no.6, pp.1710–1721, 2011.
• [4] M. Schenkel, P. Pfaeffli, W. Wilkening, D. Aemmer, and W. Fichtner, “TCAD Based Design Methodology for Substrate Current Control in Smart Power ICs”, Proc. European Solid-State Device Research Conf. (ESSDERC), 2002.
• [5] K. Fischer, K. Shenai, “The effect of parasitic bipolar transistor on the performance and reliability of scaled vertical power DMOSFETs”, Proc. of Power Electronics and Drive Systems, vol.1, pp.251, 1995.
• [6] E. Seebacher, W. Posch, K. Molnar, A. Steinmair, W. Pflanzl, B. Senapati and Z. Huszka, “Analog Compact Modeling for a 20-120V HV CMOS Technology”, Proc. NSTI Nanotechology Conf. Trade Show, vol.3, 2006.
• [7] V. Binet, Y. Savaria, M. Meunier, and Y. Gagnon, “Modeling the Substrate Noise Injected by a DC-DC Converter”, IEEE International Symposium on Circuits and Systems (ISCAS), 2007, pp.309–312.
• [8] C. Stefanucci, P. Buccella, M. Kayal, J.M. Sallese, ”Spice-compatible modeling of high injection and propagation of minority carriers in the substrate of Smart Power ICs”, Solid-State Electronics, 2014.
• [9] F. Lo Conte, J. M. Sallese, M. Pastre, F. Krummenacher, M. Kayal, “Global Modeling Strategy of Parasitic Coupled Currents Induced by Minority-Carrier Propagation in Semiconductor Substrates”, IEEE Transactions on Electron Devices, vol.57, no.1, pp. 263-272, January, 2010.
• [10] H. Zou, Y.Moursy, R. Iskander, M.M. Louerat, and J.P. Chaput, “A novel CAD framework for substrate modeling”, in 10th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME), pp. 1–4, June 2014. [11] F. Clement, E. Zysman, M. Kayal, andM. Declercq, “LAYIN: toward a global solution for parasitic couplingmodeling and visualization”, in Proc. of the IEEE Custom Integrated Circuits Conference (CICC), pp. 537–540,May 1994.
• [12] Synopsys Sentaurus Device, http://www.synopsys.com/Tools/TCAD/DeviceSimulation
• [13] N. D. Arora, J. R. Hauser, and D. J. Roulston, “Electron and hole mobilities in silicon as a function of concentration and temperature”, IEEE Trans. Electron Devices, vol. 29, pp. 292–295, February 1982.
• [14] M. E. Law, E. Solley, M. Liang, D. E. Burk, “Self-consistent model of minority-carrier lifetime, diffusion length, and mobility”, IEEE Electron Device Letters, vol. 12, pp. 401–403, August 1991.
• [15] Cadence Spectre Circuit Simulator, http://www.cadence.com/products/cic/spectre_circuit
• [16] A. Hastings,“The Art of Analog Layout”, Prentice Hall, 2005.
• [17] C. Stefanucci, P. Buccella, Y. Moursy, H. Zou, R. Iskander, M. Kayal and J.M. Sallese, “Substrate Modeling to Improve Reliability of High Voltage Technologies”, IMSTW, Paris, France, 2015.
• [18] M. Schenkel, “Substrate current effects in smart power ICs”, PhD thesis, Technische Wissenschaften ETH Zurich, 2003. Nr. 14925.