High-Performance Ternary (4:2) Compressor Based on Capacitive Threshold Logic

• Autorzy: Mirzaee R. F. , Reza A.

Identyfikatory

DOI

10.1515/eletel-2017-0048

• Języki publikacji: EN

Abstrakty

EN

This paper presents a ternary (4:2) compressor, which is an important component in multiplication. However, the structure differs from the binary counterpart since the ternary model does not require carry signals. The method of capacitive threshold logic (CTL) is used to achieve the output signals directly. Unlike the previously presented similar structure, the entire capacitor network is divided into two parts. This segregation results in higher reliability and robustness against unwanted process, voltage, and temperature (PVT) variations. Simulations are performed by HSPICE and 32nm CNFET technology. Simulation results demonstrate about 94% higher performance in terms of power-delay product (PDP) for the new design over the previous one.

Słowa kluczowe

EN

4:2 compressor; ternary logic; multiple-valued logic; CNFET; threshold logic

• Wydawca: Polish Academy of Sciences, Committee of Electronics and Telecommunication
• Czasopismo: International Journal of Electronics and Telecommunications
• Rocznik: 2017
• Tom: Vol. 63, No. 4
• Strony: 355--361
• Opis fizyczny: Bibliogr. 27 poz., schem., tab., wykr.

Twórcy

autor

Mirzaee R. F.

• Department of Computer Engineering, Shahr-e-Qods Branch, Islamic Azad University, Tehran, Iran

autor

Reza A.

• Department of Computer Engineering, Shahr-e-Qods Branch, Islamic Azad University, Tehran, Iran

Bibliografia

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Uwagi

PL

Opracowanie ze środków MNiSW w ramach umowy 812/P-DUN/2016 na działalność upowszechniającą naukę (zadania 2017).