Design of an Ultra-Low Power CT Σ∆ A/D Modulator in 65nm CMOS for Cardiac Pacemakers: From System Synthesis to Circuit Implementation

• Autorzy: Wang Y. , Cai H.

Identyfikatory

DOI

10.2478/eletel-2014-0013

• Języki publikacji: EN

Abstrakty

EN

A high performance, ultra-low power, fully differentia 2nd-order continuous-time Σ∆ analogue-to-digital modulator for cardiac pacemakers is presented in this paper. The entire design procedure is described in detail from the high-level system synthesis in both discrete and continuous-time domain, to the low-level circuit implementation of key functional blocks of the modulator. The power consumption of the designed modulator is rated at 182nA from a 1.2V power supply, meeting the ultra-low power requirement of the cardiac pacemaker applications. A 65nm CMOS technology is employed to implement the Σ∆ modulator. The modulator achieves a simulated SNR of 53.8dB over a 400 Hz signal bandwidth, with 32KHz sampling frequency and an oversampling ratio of 40. The active area of the modulator is 0.45×0.50mm².

Słowa kluczowe

EN

cardiac pacemaker; CMOS; ultra-low power; analogue-to-digital; sigma-delta modulation; continuous-time

• Wydawca: Polish Academy of Sciences, Committee of Electronics and Telecommunication
• Czasopismo: International Journal of Electronics and Telecommunications
• Rocznik: 2014
• Tom: Vol. 60, No. 1
• Strony: 109--115
• Opis fizyczny: Bibliogr. 18 poz., wykr.

Twórcy

autor

Wang Y.

• Department of Electronic Systems, Aalborg University, Niels Jernes Vej 12, 9220 Aalborg East, Denmark

autor

Cai H.

• Institut Telecom, Telecom ParisTech, 46 Rue Barrault, 75013 Paris, France

Bibliografia

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