Realization of multiplexer logic-based 2-D block firfilter using distributed arithmetic

• Autorzy: Chowdari Ch. Pratyusha , Seventline J. Beatrice

Identyfikatory

DOI

10.24423/cames.538

• Języki publikacji: EN

Abstrakty

EN

This paper presents a novel systolic two-dimensional (2D) block finite impulse response(FIR) filter architecture using a distributed arithmetic (DA)-based multiplexer look-uptable (DA-MUX-LUT). The proposed DA-MUX-LUT architecture computes the instan-taneous partial-product using the bit vector. The switching-based LUT replaces memory-based structures and reduces hardware complexity. Block processing allows memory reuse,which reduces the number of registers to store the previous input samples. Parallel addersare substituted by a modified carry look-ahead adder (MCLA), which minimizes the delay.Moreover, a resource-sharing concept is introduced to the DA-MUX-LUT block that drastically reduces the adder requirement. The application specific integrated circuit (ASIC)synthesis results show that the proposed DA-MUX-LUT-based 2-D block FIR filter forfilter size 8x8 and block size 4 has 31.22% less delay, 28.66% less area-delay product(ADP), 37.70% less power-delay product (PDP), and occupies almost the same area thanthe existing architecture.

Słowa kluczowe

EN

2-D FIR filter; switching-based LUT; distributed arithmetic; block processing

PL

2-D FIR filtr; arytmetyka rozproszona; przetwarzanie blokowe

• Wydawca: Instytut Podstawowych Problemów Techniki PAN
• Czasopismo: Computer Assisted Methods in Engineering and Science
• Rocznik: 2023
• Tom: Vol. 30, no. 1
• Strony: 89--103
• Opis fizyczny: Bibliogr. 15 poz., rys., tab.

Twórcy

autor

Chowdari Ch. Pratyusha

• Gokaraju Rangaraju Institute of Engineering and Technology, Hyderabad, India

autor

Seventline J. Beatrice

• Department of Electronics and Communication Engineering, GITAM University,Visakhapatnam, India;

Bibliografia

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• 12. C.P. Chowdari, J.B. Seventline, VLSI implementation of distributed arithmetic based block adaptive finite impulse response filter, Materials Today: Proceedings , 33 (part 7): 3757–3762, 2020, doi: 10.1016/j.matpr.2020.06.206.
• 13. C.P. Chowdari, J.B. Seventline, Low power implementation of adaptive block FIR filter design using offset binary coding, Materials Today: Proceedings , 2021, doi: 10.1016/j.matpr.2020.12.869.
• 14. V.K. Odugu, C.V. Narasimhulu, K.S. Prasad, Design and implementation of low complexity circularly symmetric 2D FIR filter architectures, Multidimensional Systems and Signal Processing , 31 : 1385–1410, 2020, doi: 10.1007/s11045-020-00714-3.
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Uwagi

Opracowanie rekordu ze środków MEiN, umowa nr SONP/SP/546092/2022 w ramach programu "Społeczna odpowiedzialność nauki" - moduł: Popularyzacja nauki i promocja sportu (2022-2023).