The versatile hardware accelerator framework for sparse vector calculations

• Autorzy: Karwatowski R. , Wiatr K.
• Języki publikacji: EN

Abstrakty

EN

In this paper, we present the advantage of the ability of FPGAs to perform various computationally complex calculations using deep pipelining and parallelism. We propose an architecture that consists of many small stream processing blocks. The designed framework maintains proper data movement and synchronization. The architecture can be easily adapted to be implemented in FPGA devices of a various size and cost - from small SoC devices to high-end PCIe accelerator cards. It is capable to perform a selected operation on a sparse data that are loaded as the stream of vectors. As an example application, we have implemented the cosine similarity measure for the text similarity calculations that uses the TF-IDF weighting scheme. The presented example application calculates the similarity of texts from the set of input documents to documents from the large database. The scheme is used to find the most similar documents. The proposed design can decrease the service time of search queries in computer centers while reducing power consumption.

Słowa kluczowe

EN

FPGA; sparse vectors; cosine similarity; Zynq; hardware accelerator

• Wydawca: Wydawnictwo PAK
• Czasopismo: Measurement Automation Monitoring
• Rocznik: 2015
• Tom: Vol. 61, No. 7
• Strony: 327--329
• Opis fizyczny: Bibliogr. 9 poz., rys., schem.

Twórcy

autor

Karwatowski R.

• AGH University of Science and Technology, 30 Mickiewicza Ave., 30-059 Krakow, Poland ACC CYFRONET AGH, 11 Nawojki St., 30-950 Krakow, Poland

autor

Wiatr K.

• AGH University of Science and Technology, 30 Mickiewicza Ave., 30-059 Krakow, Poland ACC CYFRONET AGH, 11 Nawojki St., 30-950 Krakow, Poland

Bibliografia

• [1] Lange H., Stock F., Koch A. & Hildenbrand D. (2009, April): Acceleration and energy efficiency of a geometric algebra computation using reconfigurable computers and GPUs. In Field-Programmable Custom Computing Machines, 2009. FCCM'09. 17th IEEE Symposium on (pp. 255-258). IEEE.
• [2] Jamro E., Pabiś T., Russek P. & Wiatr K. (2014): The algorithms for FPGA implementation of sparse matrices multiplication. Computing & Informatics, 33(3).
• [3] Smailbegovic F. S., Gaydadjiev G. N. & Vassiliadis S. (2005, November): Sparse matrix storage format. In Proceedings of the 16th Annual Workshop on Circuits, Systems and Signal Processing, ProRisc 2005 (pp. 445-448).
• [4] Sun S., Monga M., Jones P. H. & Zambreno J. (2012): An I/O Bandwidth-Sensitive Sparse Matrix-Vector Multiplication Engine on FPGAs. Circuits and Systems I: Regular Papers, IEEE Transactions on, 59(1), 113-123.
• [5] Zou D., Dou Y., Guo S. & Ni S. (2013): High performance sparse matrix-vector multiplication on FPGA. IEICE Electronics Express, 10(17), 20130529-20130529.
• [6] Kiela D. & Clark S. (2014, April): A systematic study of semantic vector space model parameters. In Proceedings of the 2nd Workshop on Continuous Vector Space Models and their Compositionality (CVSC) at EACL (pp. 21-30).
• [7] http://www.xilinx.com/products/silicon-devices/soc/zynq-7000.html
• [8] http://xillybus.com/doc
• [9] http://www.xilinx.com/products/silicon-devices/fpga/virtex-7.html