FPGA emulator of switched reluctance motor in a FIL structure

• Autorzy: Fabiański B.
• Konferencja: Computer Applications in Electrical Engineering (18-19.04.2016 ; Poznań, Polska)
• Języki publikacji: EN

Abstrakty

EN

The use of FPGA platform in power section emulation of switched reluctance motor is presented in the article. Emulation of the power part gives many advantages in the means of rapid prototyping. Power section of the electric drive is expensive and thus need to be protected from damage. Evaluating of complicated control algorithms gives a risk to damage in the real system even if some simulation tests were made before. Introducing FPGA in the loop gives opportunity to minimize such a failure. FIL system would be time efficient when using new features of CAD/CAM simulation systems that are able to convert selected part of the system model to the FPGA environment. The article presents this process in the example of SRM drive. Model equation and its block structure are introduced. Then the way to the FIL implementation in details is shown with appropriate IDE configuration, block model adaptation and run example.

Słowa kluczowe

EN

FPGA; FIL; rapid prototyping; modelling; SRM; HDL coder; control system; electric drive; cosimulation

• Wydawca: Wydawnictwo Politechniki Poznańskiej
• Czasopismo: Poznan University of Technology Academic Journals. Electrical Engineering
• Rocznik: 2016
• Tom: No. 87
• Strony: 289--300
• Opis fizyczny: Bibliogr. 9 poz., rys.

Twórcy

autor

Fabiański B.

• Poznan University of Technology

Bibliografia

• [1] Fabianski B., Energetic Properties of a New, Iron Powder Based Switched Reluctance Motor Drive, Mechatronics 2013 (2014): 331-38.
• [2] Fabianski B., Zawirski K., Switched Reluctance Motor Drive Embedded Control System, Mechatronics 2013 (2014): 339-46.
• [3] Deskur J., Maciejuk A. Modelling of Switched Reluctance Motor Drive, XIX Symposium on Electromagnetic Phenomena in Nonlinear Circuits (EPNC), Proceedings of (2006): pp. 159-160.
• [4] Dufour C., V. Lapointe, et al., Hardware-in-the-Loop Closed-Loop Experiments with an FPGA-Based Permanent Magnet Synchronous Motor Drive System and a Rapidly Prototyped Controller, IEEE International Symposium on Industrial Electronics, 2008. ISIE 2008. N.p., 2008, pp. 2152-2158.
• [5] Dufour C., Paquin J.-N., et al. Specifications for Real-Time Simulation of Switched Reluctance Drives Using Microprocessors and FPGAs as Computational Engines, Electric Machines and Drives Conference, 2009. IEMDC ’09. IEEE International, N.p., 2009. pp. 750-754.
• [6] Kelly P.B., A New Class of Test Instrument: The FPGA Based Module, 2012 IEEE AUTOTESTCON. N.p., 2012. pp. 269-271.
• [7] Kula S., Implementation of the Open-Software Models of Switched Reluctance Motor on Model-in-the-Loop Platform, 2015 XXV International Conference on Information, Communication and Automation Techn.(ICAT), N.p., 2015, pp. 1-6.
• [8] Orlowska-Kowalska T., Kaminski M., FPGA Implementation of the Multilayer Neural Network for the Speed Estimation of the Two-Mass Drive System, IEEE Transactions on Industrial Informatics 7.3 (2011): pp. 436-445.
• [9] Penczek A., Stala R., Stawiarski Ł., Szarek M., Hardware-in-the-Loop FPGA-based Simulations of Switch - mode Converters for Research and Eucational Purposes, Przegląd Elektrotechniczny, vol. R. 87, nr 11, 2011, pp. 194-200.

Uwagi

Opracowanie ze środków MNiSW w ramach umowy 812/P-DUN/2016 na działalność upowszechniającą naukę.