Method of performing Design FMEA on electronic circuit diagrams

• Autorzy: Karcz R.
• Języki publikacji: EN

Abstrakty

EN

Existing method of performing FMEA for electronic diagrams is time consuming task. For complex systems analysis of every single component failure mode and its effect deeply involves design team and blocks resources availability for long time. Method presented in this paper allows effective analysis of design failure modes using FMEA approach carrying so called Time to Acceptable Analysis (TTAA) constraint.

Słowa kluczowe

EN

electronic circuit analysis; failure mode; TTAA

• Wydawca: Polskie Towarzystwo Bezpieczeństwa i Niezawodności
• Czasopismo: Journal of Polish Safety and Reliability Association
• Rocznik: 2015
• Tom: Vol. 6, No. 1
• Strony: 125--128
• Opis fizyczny: Bibliogr. 4 poz., rys., tab., wykr.

Twórcy

autor

Karcz R.

• ABB, Kraków, Poland

Bibliografia

• [1] Bluvband, Z., Polak, R. & Grabov, P. (2014). Bouncing Failure Analysis (BFA): The Unified FTA-FMEA Methodology, http://aldservice.com/en/articles/ bouncing-failure-analysis-bfa-the-unified-ftafmea-method.html [access: 16 January 2014]
• [2] IEC-60812:2006 Second edition. Analysis techniques for system reliability – Procedure for failure mode
• [3] IEC-61709 Edition 2.0 (2011-06). Electric components – Reliability – Reference conditions for failure rates and stress models for conversion
• [4] FMD 2013. Failure Modes/Mechanism Distributions. Reliability Information Analysis Center (RIAC)