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Poprawa dokładności symulacji systemów wielordzeniowych za pomocą modelowania behawioralnego
Języki publikacji
Abstrakty
Many studies undertaken to date realize that the CPU performance does not scale linearly as the number of CPU cores increases. Several models seek to quantify the performance of multi-core systems. However, these models have a set of limitations and cannot accurately predict the real speedup of a given system. Therefore, other kinds of models can be helpful. In the paper we first set up and validate a simulation environment in order to evaluate multi-core systems, and second we propose and test a refined model that significantly improves performance predictions.
Wiele dotychczasowych badan wykazuje, że wydajność procesora nie skaluje się liniowo wraz ze wzrostem liczby rdzeni procesora. Przedstawiono kilka modeli umozliwiających ilosciowe określenie wydajności system w wielordzeniowych. Jednak modele te mają szereg ograniczeń i nie mogą dokładnie przewidziec rzeczywistości przyspieszenie danego systemu. Dlatego pomocne mogą byc inne rodzaje modeli. W artykule ´ najpierw skonfigurowalismy i sprawdziliśmy kolejno środowisko symulacji do oceny system w wielordzeniowych, a następnie proponujemy i testujemy udoskonalony model, który znacznie poprawia prognozy wydajności.
Wydawca
Czasopismo
Rocznik
Tom
Strony
139--145
Opis fizyczny
Bibliogr. 21 poz., tab.
Twórcy
autor
- Federal University of Technology - Paraná (UTFPR), Av. Sete de Setembro 3165, 80230-901, Curitiba (PR) - Brazil
- Federal University of Technology - Paraná (UTFPR), Av. Sete de Setembro 3165, 80230-901, Curitiba (PR) - Brazil
Bibliografia
- [1] D. Puchala, M. Yatsymirskyy, B. Szczepaniak, and K. Stokfiszewski, “Effectiveness of Fast Fourier Transform Implementations on GPU and CPU,” Przeglad Elektrotechniczny, vol. 2016, no. 7, pp. 69–71, 2016.
- [2] M. Cegielski, “Parallel computation of transient processes on OpenCL framework,” Przeglad Elektrotechniczny, vol. 2016, no. 7, pp. 75–78, 2016.
- [3] G. M. Amdahl, “Validity of the single processor approach to achieving large scale computing capabilities,” in AFIPS spring joint computer conference, 1967.
- [4] J. Gustafson, “Reevaluating Amdahl’s law,” in Communications ACM, May 1988, pp. 532–533, doi: 10.1145/42411.42415.
- [5] M. D. Hill and M. R. Marty, “Amdahl’s law in the multi-core era,” Computer, vol. 41, no. 7, pp. 33–38, July 2008.
- [6] X. H. Sun and L. M. Ni, “Another view on parallel speedup,” in Proceedings Supercomputing ’90, Nov 1990, pp. 324–333.
- [7] X.-H. Sun and Y. Chen, “Reevaluating Amdahl’s law in the multicore era,” J. Parallel Distrib. Comput., vol. 70, no. 2, pp. 183– 188, Feb. 2010, doi: 10.1016/j.jpdc.2009.05.002.
- [8] A. Kandalintsev and R. Lo Cigno, “A behavioral first order CPU performance model for clouds’ management,” in International Congress on Ultra Modern Telecommunications and Control Systems and Workshops, 10 2012, pp. 40–48.
- [9] R. N. Calheiros, R. Ranjan, A. Beloglazov, C. A. F. De Rose, and R. Buyya, “CloudSim: A toolkit for modeling and simulation of cloud computing environments and evaluation of resource provisioning algorithms,” Softw. Pract. Exper., vol. 41, no. 1, pp. 23–50, Jan. 2011, doi: 10.1002/spe.995 .
- [10] E. Track, N. Forbes, and G. Strawn, “The end of Moore’s law,” Computing in Science Engineering, vol. 19, no. 2, pp. 4–6, Mar 2017, doi: 10.1109/MCSE.2017.25.
- [11] B. Juurlink and C. H. Meenderinck, “Amdahl’s Law for Predicting the Future of Multicores Considered Harmful,” SIGARCH Comput. Archit. News, vol. 40, no. 2, pp. 1–9, May 2012.
- [12] L. A. Barroso, S. Iman, M. Dubois, and K. Ramamurthy, “RPM: a rapid prototyping engine for multiprocessor systems,” Computer, vol. 28, no. 2, pp. 26–34, Feb. 1995.
- [13] A. K. Nanda, K.-K. Mak, K. Sugavanam, R. Sahoo, V. Soundararajan, and T. B. Smith, “MemorIES: A programmable, real-time hardware emulation tool for multiprocessor server design,” vol. 35, 2000.
- [14] R. A. Bergamaschi, I. Nair, G. Dittmann, H. D. Patel, G. Janssen, N. Dhanwada, A. Buyuktosunoglu, E. Acar, G.-J. Nam, D. Kucar, P. Bose, J. A. Darringer, and G. Han, “Performance modeling for early analysis of multi-core systems,” in 5th IEEE/ACM/IFIP CODES+ISSS, 2007.
- [15] J. Wenjie Jiang, T. Lan, S. Ha, M. Chen, and M. Chiang, “Joint VM placement and routing for data center traffic engineering,” pp. 2876–2880, 3 2012, doi: 10.1109/INFCOM.2012.6195719 .
- [16] V. Shrivastava, P. Zerfos, K.-w. Lee, H. Jamjoom, Y.-H. Liu, and S. Banerjee, “Application-aware virtual machine migration in data centers,” in Proceedings - IEEE INFOCOM, 2011.
- [17] C. Tang, M. Steinder, M. Spreitzer, and G. Pacifici, “A scalable application placement controller for enterprise data centers,” in 16th InternationalWorld WideWeb Conference, WWW2007, 01 2007, pp. 331–340, doi: 10.1145/1242572.1242618 .
- [18] M. Feldman, K. Lai, and l. Zhang, “The proportionalshare allocation market for computational resources,” IEEE Transactions on Parallel and Distributed Systems, vol. 20, pp. 1075 – 1088, 09 2009, doi: 10.1109/TPDS.2008.168 .
- [19] A. Kandalintsev, “Application interference in multi-core architectures: Analysis and effects,” Ph.D. Thesis, Universita degli Studi di Trento, Italy, Department of Information Engineering and Computer Science, Apr. 2016.
- [20] D. Zaparanuks, M. Jovic, and M. Hauswirth, “Accuracy of performance counter measurements,” in Proc. of IEEE ISPASS, Boston, Massachusetts, USA, April 26-28 2009, pp. 23–32.
- [21] V. M. Weaver and J. Dongarra, “Can hardware performance counters produce expected, deterministic results,” in 3rd Workshop on Functionality of Hardware Performance Monitoring, Atlanta, GA, 12-2010 2010.
Uwagi
Opracowanie rekordu ze środków MNiSW, umowa Nr 461252 w ramach programu "Społeczna odpowiedzialność nauki" - moduł: Popularyzacja nauki i promocja sportu (2021).
Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-571625c8-dfa5-4dd4-b4bf-999bb1680cab