New Structure of Test Pattern Generator Stimulating Crosstalks in Bus-type Connections

• Autorzy: Garbolino T.

Identyfikatory

DOI

10.1515/eletel-2015-0009

• Języki publikacji: EN

Abstrakty

EN

The paper discloses the idea of a new structure for a Test Pattern Generator (TPG) for detection of crosstalk faults that may happen to bus-type interconnections between built in blocks within a System-on-Chip structure. The new idea is an improvement of the TPG design proposed by the author in one of the previous studies. The TPG circuit is meant to generate test sequences that guarantee detection of all crosstalk faults with the capacitive nature that may occur between individual lines within an interconnecting bus. The study comprises a synthesizable and parameterized model developed for the presented TPG in the VLSI Hardware Description Language (VHDL) with further investigation of properties and features of the offered module. The significant advantages of the proposed TPG structure include less area occupied on a chip and higher operation frequency as compared to other solutions. In addition, the design demonstrates good scalability in terms of both the hardware overhead and the length of the generated test sequence.

Słowa kluczowe

EN

integrated circuit interconnections; crosstalk; test pattern generator; built-in self-test; system-on-a-chip

• Wydawca: Polish Academy of Sciences, Committee of Electronics and Telecommunication
• Czasopismo: International Journal of Electronics and Telecommunications
• Rocznik: 2015
• Tom: Vol. 61, No. 1
• Strony: 67--75
• Opis fizyczny: Bibliogr. 38 poz., rys., tab.

Twórcy

autor

Garbolino T.

• Faculty of Automatic Control, Electronics and Computer Science, Silesian University of Technology, Gliwice, Poland

Bibliografia

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