Design for reliability: delay faults modeling and simulation for CMOS flip-flops

• Autorzy: Cai H. , Liu K. , An T , Naviner L
• Języki publikacji: EN

Abstrakty

EN

Continuously scaling down of CMOS technology brings on low power but also reliability problems such as aggravated aging effects and process variations. They can influence and degrade the performance of integrated circuits. In recent years, reliability issues of 65nm CMOS node has been intensively studied. In this work, a reliability assessment approach considering aging mechanisms and parametric process variation induced delay fault is proposed in design loop. Negative bias temperature instability (NBTI) and hot carrier injection (HCI) induced degradation are simulated in 65nm flip-flops with different architectures. An example with simple combinational logic (65nm full adder) illustrates this approach for fault probability. It is concluded that process variations are more important comparing to aging effects induced degradation when designing low power digital flip-flops.

Słowa kluczowe

EN

aging mechanism; process variations; flip-flops; delay faults

PL

mechanizm starzenia; zmiany procesu; przerzutnik; uszkodzenia opóźnieniowe

• Wydawca: Lodz University of Technology. Department of Microelectronics and Computer Science
• Czasopismo: International Journal of Microelectronics and Computer Science
• Rocznik: 2014
• Tom: Vol. 5, nr 3
• Strony: 98--104
• Opis fizyczny: Bibliogr. 15 poz.

Twórcy

autor

Cai H.

• Département Communications et Electronique, Institut Mines-Télécom, Télécom-ParisTech, LTCI-CNRS-UMR 5141, Paris CEDEX l3, 75634, France

autor

Liu K.

• Département Communications et Electronique, Institut Mines-Télécom, Télécom-ParisTech, LTCI-CNRS-UMR 5141, Paris CEDEX l3, 75634, France

autor

An T

• Département Communications et Electronique, Institut Mines-Télécom, Télécom-ParisTech, LTCI-CNRS-UMR 5141, Paris CEDEX l3, 75634, France

autor

Naviner L

• Département Communications et Electronique, Institut Mines-Télécom, Télécom-ParisTech, LTCI-CNRS-UMR 5141, Paris CEDEX l3, 75634, France

Bibliografia

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