A Method to Support Diagnostics of Dynamic Faults in Networks of Interconnections

• Autorzy: Garbolino T.

Identyfikatory

DOI

10.24425/123540

• Języki publikacji: EN

Abstrakty

EN

The article is devoted to the method facilitating the diagnostics of dynamic faults in networks of interconnection in systems-on-chips. It shows how to reconstruct the erroneous test response sequence coming from the faulty connection based on the set of signatures obtained as a result of multiple compaction of this sequence in the MISR register with programmable feedback. The Chinese reminder theorem is used for this purpose. The article analyzes in detail the various hardware realizations of the discussed method. The testing time associated with each proposed solution was also estimated. Presented method can be used with any type of test sequence and test pattern generator. It is also easily scalable to any number of nets in the network of interconnections. Moreover, it supports finding a trade-off between area overhead and testing time.

Słowa kluczowe

EN

network of interconnections; system-on-chip; diagnostics; MISR; compaction; signature; Chinese remainder theorem

• Wydawca: Polish Academy of Sciences, Committee of Electronics and Telecommunication
• Czasopismo: International Journal of Electronics and Telecommunications
• Rocznik: 2018
• Tom: Vol. 64, No. 3
• Strony: 407--420
• Opis fizyczny: Bibliogr. 20 poz., rys., tab.

Twórcy

autor

Garbolino T.

• Faculty of Automatic Control, Electronics and Computer Science, Silesian University of Technology, Gliwice, Poland

Bibliografia

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Uwagi

1. Opracowanie rekordu w ramach umowy 509/P-DUN/2018 ze środków MNiSW przeznaczonych na działalność upowszechniającą naukę (2018).

2. This work was supported by the Ministry of Science and Higher Education funding for statutory activities (BK-220/RAu-3/2016, BK-232/RAu-3/2017).