Employing FPGA DSP blocks for time-to-digital conversion

• Autorzy: Kwiatkowski Paweł

Identyfikatory

DOI

10.24425/mms.2019.130570

• Języki publikacji: EN

Abstrakty

EN

The paper presents a novel implementation of a time-to-digital converter (TDC) in field-programmable gate array (FPGA) devices. The design employs FPGA digital signal processing (DSP) blocks and gives more than two-fold improvement in mean resolution in comparison with the common conversion method (carry chain-based time coding line). Two TDCs are presented and tested depending on DSP configuration. The converters were implemented in a Kintex-7 FPGA device manufactured by Xilinx in 28 nm CMOS process. The tests performed show possibilities to obtain mean resolution of 4.2 ps but measurement precision is limited to at most 15 ps mainly due to high conversion nonlinearities. The presented solution saves FPGA programmable logic blocks and has an advantage of a wider operation range when compared with a carry chain-based time coding line.

Słowa kluczowe

EN

time-to-digital converter; time coding line; time interval counter; digital signal processing; field-programmable gate array

• Wydawca: Komitet Metrologii i Aparatury Naukowej PAN
• Czasopismo: Metrology and Measurement Systems
• Rocznik: 2019
• Tom: Vol. 26, nr 4
• Strony: 631--643
• Opis fizyczny: Bibliogr. 46 poz., rys., tab., wzory

Twórcy

autor

Kwiatkowski Paweł

• Military University of Technology, Faculty of Electronics, Gen. S. Kaliskiego 2, 00-908 Warsaw, Poland

Bibliografia

• [1] Longfei, K., Zhao, L., Zhou, J., Liu, S., Qi, A. (2013). A 128-Channel High Precision Time Measurement Module. Metrol. Meas. Syst., 20(2), 275-286.
• [2] Arkani, M. (2015). A High Performance Digital Time Interval Spectrometer: An Embedded, FPGA-Based System With Reduced Dead Time Behaviour. Metrol. Meas. Syst., 22(4), 601-609.
• [3] Kurtti, S., Nissinen, J., Jansson, J.-P., Kostamovaara, J. (2018). A CMOS chip set for accurate pulsed time-of-flight laser range finding. Proc. IEEE I2MTC 2018, Houston, Texas, United States.
• [4] Grzelak, S., Czoków, J. Kowalski, M., Zieliński, M. (2014). Ultrasonic Flow Measurement with High Resolution. Metrol. Meas. Syst., 21(2), 305-316.
• [5] Won, J. Y., Lee, J. S. (2018). Highly Integrated FPGA-Only Signal Digitization Method Using Single-Ended Memory Interface Input Receivers for Time-of-Flight PET Detectors. IEEE Trans. Biomed. Circuits Syst., 12(6), 1401-1409.
• [6] Krehlik, P., Śliwczyński, L., Buczek, L., Kołodziej, J., Lipiński, M. (2016). ELSTAB – Fiber-optic time and frequency distribution technology: A general characterization and fundamental limits. IEEE Trans. Ultrason., Ferroelectr., Freq. Control., 63(7), 993-1004.
• [7] Fries, M. D., Williams, J. J. (2002). High-Precision TDC in an FPGA using a 192-MHz Quadrature Clock. Proc. IEEE NSS/MIC 2002, Norfolk, Virginia, United States, 580-584.
• [8] Won, J. Y., Kwon, S. I., Yoon, H. S., Ko, G. B., Son, J.-W. Lee, J. S. (2016). Dual-Phase Tapped-Delay-Line Time-to-Digital Converter With On-the-Fly Calibration Implemented in 40 nm FPGA. IEEE Trans. Biomed. Circuits Syst., 10(1), 231-242.
• [9] Grzęda, G., Szplet, R. (2016). Time interval measurement module implemented in SoC FPGA device. International Journal of Electronics and Telecommunications, 62(3), 237-246.
• [10] Chaberski, D. (2016). Time-to-digital-converter based on multiple-tapped-delay-line. Measurement, 89, 87-96.
• [11] Won, J. Y., Lee, J. S. (2016). Time-to-Digital Converter Using a Tuned-Delay Line Evaluated in 28-, 40-, and 45-nm FPGAs. IEEE Trans. Instrum. Meas., 65(7), 1678-1689.
• [12] Szplet, R., Sondej, D., Grzęda, G. (2016). High-Precision Time Digitizer Based on Multiedge Coding in Independent Coding Lines. IEEE Trans. Instrum. Meas., 65(8), 1884-1894.
• [13] Szplet, R., Kwiatkowski, P., Jachna, Z., Różyc, K. (2016). An Eight-Channel 4.5-ps Precision Timestamps-Based Time Interval Counter in FPGA Chip. IEEE Trans. Instrum. Meas., 65(9), 2088-2100.
• [14] Chen, P., Hsiao, Y.-Y., Chung, Y.-S., Tsai, W. X., Lin, J.-M. (2017). A 2.5-ps Bin Size and 6.7-ps Resolution FPGA Time-to-Digital Converter Based on Delay Wrapping and Averaging. IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 25(1), 114-124.
• [15] Cui, K., Ren, Z., Li, X., Liu, Z., Zhu, R. (2017). A High-Linearity, Ring-Oscillator-Based, Vernier Time-to-Digital Converter Utilizing Carry Chains in FPGAs. IEEE Trans. Nucl. Sci., 64(1), 697-704.
• [16] Chaberski, D., Frankowski, R., Gurski, M., Zieliński, M. (2017). Comparison of Interpolators Used for Time-Interval Measurement Systems Based on Multiple-Tapped Delay Line. Metrol. Meas. Syst., 24(2), 401-412.
• [17] Wang, Y., Kuang, J., Liu, C., Cao, Q. (2017). A 3.9-ps RMS Precision Time-to-Digital Converter Using Ones-Counter Encoding Scheme in a Kintex-7 FPGA. IEEE Trans. Nucl. Sci., 64(10), 2713-2718.
• [18] Szplet, R., Kwiatkowski, P., Różyc, K., Jachna, Z., Sondej, T. (2017). Picosecond-precision multichannel autonomous time and frequency counter. Rev. Sci. Instrum., 88(12), 125101/1-12.
• [19] Pałka. M., et al. (2017). Multichannel FPGA based MVT system for high precision time (20 ps RMS) and charge measurement. J. Instrum., 12(8), P08001/1-10.
• [20] Sano, Y., Horii, Y., Ikeno, M., Sasaki, O., Tomoto, M., Uchida, T. (2017). Subnanosecond time-to-digital converter implemented in a Kintex-7 FPGA. Nucl. Instrum. Methods Phys. Res. A, 874, 50-56.
• [21] Zhang, J., Zhou, D. (2018). An 8.5-ps Two-Stage Vernier Delay-Line Loop Shrinking Time-to-Digital Converter in 130-nm Flash FPGA. IEEE Trans. Instrum. Meas., 67(2), 406-414.
• [22] Chen, H., Li, D.-U. (2019). Multichannel, Low Nonlinearity Time-to-Digital Converters Based on 20 and 28 nm FPGAs. IEEE Trans. Ind. Electron., 66(4), 3265-3274.
• [23] Cao, G., Xia, H., Dong, N. (2019). A 6.6 ps RMS resolution time-to-digital converter using interleaved sampling method in a 28 nm FPGA. Rev. Sci. Instrum., 90(4), 044706/1-8.
• [24] Lusardi,N., Garzetti, F., Geraci, A. (2019). Digital instrument with configurable hardware and firmware for multi-channel time measures. Rev. Sci. Instrum., 90(5), 055113/1-13.
• [25] Kwiatkowski, P., Szplet, R. (2019). Time-to-Digital Converter with Pseudo-Segmented Delay Line. Proc. IEEE I2MTC 2019, Auckland, New Zealand.
• [26] Carbone, P., Kiaei, S., Xu, F. (2014). Design, Modeling and Testing of Data Converters. Springer Berlin Heidelberg.
• [27] Wu, J., Shi, Z.,Wang, I. Y. (2003). Firmware-only implementation of Time-to-Digital Converter (TDC) in field-programmable gate array (FPGA). IEEE Nucl. Sci. Symp. Conf. Rec. 2003, Portland, Oregon, United States, 177-181.
• [28] Wu, J., Shi, Z. (2008). The 10-ps wave union TDC: Improving FPGA TDC resolution beyond its cel delay. Proc. IEEE NSS/MIC 2008, Dresden, Germany, 3440-3446.
• [29] Aloisio, A., Branchini, P., Cicalese, R., Giordano, R., Izzo, V., Loffredo, S. (2007). FPGA implementation of a high-resolution time-to-digital converter. Proc. IEEE NSS/MIC 2007, Honolulu, Hawaii, United States, 504-507.
• [30] Wang, H., Zhang, M., Yao, Q. (2013). A new realization of time-to-digital converters based on FPGA internal routing resources. IEEE Trans. Ultrason., Ferroelectr., Freq. Control., 60(9), 17887-1795.
• [31] Szplet, R., Klepacki, K. (2010). An FPGA-integrated time-to-digital converter based on two-stage pulse shrinking. IEEE Trans. Instrum. Meas., 59(6), 1663-1670.
• [32] Wang, Y., Liu, C., Zhu, W. (2013). Two novel designs of multi-phase clocked ultra-high speed time counter on FPGA for TDC implementation. Proc. of IEEE NSS/MIC 2013, Seoul, South Korea, 1082-3654.
• [33] Bogdan, M., et al. (2005). A96-channel FPGA-based Time-to-Digital Converter (TDC) and fast trigger processor module with multi-hit capability and pipeline. Nucl. Instrum. Methods Phys. Res. A, 554, 444-457.
• [34] Arpin, L., Bergeron, M., Tetrault, M.-A., Lecomte, R., Fontaine, R. (2009). A Sub-Nanosecond Edge Detection System using embedded FPGA fabrics. Proc. IEEE-NPSS Real Time Conf. 2009, Beijing, China, 299-303.
• [35] Imrek, J., Hegyesi, G., Kalinka, G., Molnar, J., Nagy, F., Valastyan, I., Szabo, Z. (2010). FPGA based TDC using Virtex-4 ISERDES blocks. Proc. NSS/MIC 2010, Knoxville, Tennessee, United States, 1413-1415.
• [36] Xiang, T., Zhao, L., Jin, X., Wang, T., Chu, S., Ma, C., Liu, S., An, Q. (2014). A 56-ps multi-phase clock time-to-digital convertor based on Artix-7 FPGA. Proc. IEEE-NPSS Real Time Conf. 2014, Nara, Japan.
• [37] Tancock, S., Arabul, E., Dahnoun, N., Mehmood, S. (2018). Can DSP48A1 adders be used for high-resolution delay generation? Proc. MECO 2018, Budva, Montenegro.
• [38] Tancock, S., Dahnoun, N. (2019). A 5.25 ps-resolution TDC on FPGA using DSP blocks. Proc. DISP 2019, Oxford, United Kingdom.
• [39] Salomon, R., Joost, R. (2009). BOUNCE: A New High-Resolution Time-Interval Measurement Architecture. IEEE Embedded Syst. Lett., 1(2), 56-59.
• [40] 7 Serie DSP48E1 Slice. User Guide UG479, v1.10, Xilinx. https://www.xilinx.com/support/documentation/user_guides/ug479_7Series_DSP48E1.pdf (Mar. 2018)
• [41] Cova, S., Bertolaccini, M. (1970). Differential linearity testing and precision calibration of multichannel time sorters. Nucl. Instrum. Methods, 77(2), 269-276.
• [42] 7 Series FPGAs Configurable Logic Block. User Guide UG474, v1.8, Xilinx. https://www.xilinx.com/support/documentation/user_guides/ug474_7Series_CLB.pdf (Sep. 2016)
• [43] Kwiatkowski, P., Różyc, K., Sawicki, M., Jachna, Z., Szplet, R. (2017). 5 ps jitter programmable time interval/frequency generator. Metrol. Meas. Syst., 24(1), 57-68.
• [44] Szplet, R., Jachna, Z., Kwiatkowski, P., Różyc, K. (2013). A 2.9 ps equivalent resolution interpolating time counter based on multiple independent coding lines. Meas. Sci. Technol., 24(7), 035904/1-15.
• [45] Wu, J. (2014). Uneven BinWidth Digitization and a Timing Calibration Method Using Cascaded PLL. Proc. IEEE-NPSS Real Time Conf. 2014, Nara, Japan.
• [46] Szplet, R., Szymanowski, R., Sondej, D. (2019). Measurement Uncertainty of Precise Interpolating Time Counters. IEEE Trans. Instrum. Meas., 68(11), 4348-4356.

Uwagi

EN

This work has been supported by the Military University of Technology, Warsaw, Poland, as a part of the project PBS 661.