Error analysis of digital filters using fixed point arithmetic

• Autorzy: Wirski Robert , Poczekajło Paweł

Identyfikatory

DOI

10.24425/ijet.2025.153611

• Języki publikacji: EN

Abstrakty

EN

Based on an electrocardiogram filter, measurement methods of magnitude and phase responses, quantization and overflow errors, as well as limit circles in digital filters for fixed number representation are presented. A computer library for SCILAB has been created to simplify simulations. Direct form II, cascade, and rotation structures performance has been compared. It has been shown that there is no the best structure but the rotation one is superior to classical structures except for quantization errors. However, due to its low overflow errors, quantization noise can be further minimised by relocation of integer bits to fractional part of fixed point number representation.

Słowa kluczowe

EN

digital signal processing; finite word length effects; simulation; quantization; overflow

• Wydawca: Polish Academy of Sciences, Committee of Electronics and Telecommunication
• Czasopismo: International Journal of Electronics and Telecommunications
• Rocznik: 2025
• Tom: Vol. 71, No. 3
• Strony: 22
• Opis fizyczny: Bibliogr. 17 poz., rys., tab.

Twórcy

autor

Wirski Robert

• Koszalin University of Technology, Koszalin, Poland

• https://orcid.org/0000-0002-1654-2109

autor

Poczekajło Paweł

• Koszalin University of Technology, Koszalin, Poland

• https://orcid.org/0000-0003-4742-7872

Bibliografia

• [1] A. Antoniou, Digital Signal Processing, McGraw-Hill, 2006.
• [2] K.-I. Kum, W. Sung, Combined word-length optimization and high-level synthesis of digital signal processing systems, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 20 (8) (2001) 921-930. https://doi.org/10.1109/43.936374.
• [3] G. Constantinides, P. Cheung, W. Luk, Wordlength optimization for linear digital signal processing, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 22 (10) (2003) 1432-1442. https://doi.org/10.1109/TCAD.2003.818119.
• [4] G. Li, L. Meng, Z. Xu, J. Hua, A novel digital filter structure with minimum roundoff noise, Digital Signal Processing 20 (4) (2010) 1000-1009. https://doi.org/10.1016/j.dsp.2009.10.018.
• [5] V. L. R. da Costa, H. V. Schettino, ˆAndrei Camponogara, F. P. de Campos, M. V. Ribeiro, Digital filters for clustered-OFDM-based PLC systems: Design and implementation, Digital Signal Processing 70 (2017) 166-177. https://doi.org/10.1016/j.dsp.2017.08.004.
• [6] J. Paduart, J. Schoukens, Y. Rolain, Fast measurement of quantization distortions in DSP algorithms, IEEE Transactions on Instrumentation and Measurement 56 (5) (2007) 1917-1923. https://doi.org/10.1109/TIM.2007.903644.
• [7] A. Volkova, M. Istoan, F. De Dinechin, T. Hilaire, Towards hardware IIR filters computing just right: Direct form I case study, IEEE Transactions on Computers 68 (4) (2019) 597-608. https://doi.org/10.1109/TC.2018.2879432.
• [8] H. H. Thannoon, I. A. Hashim, Efficient fpga implementation of recur-sive least square adaptive filter using non-restoring division algorithm, International Journal of Electronics and Telecommunications 69 (4) (2024) 175-182. http://dx.doi.org/10.24425/ijet.2023.147705.
• [9] P. Poczekajlo, An Overview of the Methods of Synthesis, Realization and Implementation of Orthogonal 3-D Rotation Filters and Possibilities of Further Research and Development, International Journal of Electronics and Telecommunications 67 (2) (2021) 295-300. https://dx.doi.org/10.24425/ijet.2021.135979.
• [10] R. Wirski, Synthesis and realization of two-dimensional separable denominator orthogonal systems via decomposition into 1-D systems, IEEE Transactions on Circuits and Systems I: Regular Papers 66 (11) (2019) 4309-4322. https://doi.org/10.1109/TCSI.2019.2927673
• [11] K. D. Shinde, D. Khanapure, N. Shetti, J. Athavani, N. Hattiholi, Denoising of ECG signal using optimized IIR filter architecture—a CSD-based design, in: S. Kalya, M. Kulkarni, S. Bhat (Eds.), Advances in VLSI, Signal Processing, Power Electronics, IoT, Communication and Embedded Systems, Springer Nature Singapore, Singapore, 2024, pp. 143-157.
• [12] R. Wu, X. Tang, J. He, Y. Cao, L. Xiao, F. Xiao, The DST-O method for multiband IIR filter, Circuits, Systems, and Signal Processing 42 (2023) 431-448. https://doi.org/10.1007/s00034-022-02129-w.
• [13] The SCILAB homepage, http://www.scilab.org.
• [14] A. Fettweis, Digital filter structures related to classical filter networks, AE ¨U 25 (2) (1971) 79-89.
• [15] E. Depretere, P. Dewilde, Orthogonal cascade realization of real multi-port digital filters, Int. J. Circuits Theory Appl. 8 (1980) 245-272.
• [16] P. Poczekajlo, R. Wirski, Synthesis and realization of 3-D or-thogonal FIR filters using pipeline structures, Circuits Syst Signal Process 37 (2018) 1669-1691. https://doi.org/10.1007/s00034-017-0618-2.
• [17] G. H. Golub, C. F. Van Loan, Matrix Computations, 4th Edition, The Johns Hopkins Univ. Press, Baltimore, MD, 1996.

Uwagi

Opracowanie rekordu ze środków MNiSW, umowa nr POPUL/SP/0154/2024/02 w ramach programu "Społeczna odpowiedzialność nauki II" - moduł: Popularyzacja nauki (2025).