Design and implementation of parallel multiplier using two split circuits

• Autorzy: Alkurwy Salah Hasan Ibrahim

Identyfikatory

DOI

10.15199/48.2021.07.04

Warianty tytułu

PL

Projektowanie i implementacja równoległego mnożnika przy użyciu dwóch obwodów rozdzielonych

• Języki publikacji: EN

Abstrakty

EN

A novel binary parallel multiplier circuit is designed and implemented in this study. The proposed multiplier is a combination of two split circuits, namely, truncated multiplier and least-significant bit (LSB) circuit. The LSB multiplier is designed based on the Vedic mathematic expression, but some modification is made for it to be compatible with the truncated multiplier and to achieve correct results for all the multiplication values. The designed circuit is coded by the Verilog hardware description language (HDL) using Quartus II. The register transfer level is verified, and the gate level is simulated using the Cyclone IV field programmable gate array (FPGA) platform. The proposed multiplier operates at 107.5 MHz frequency operating speed and requires 155 combinational logics. Comparison with other reported works shows that the proposed design has 19.5% less delay time. The new parallel multiplier is suitable for applications in various electronic devices due to its good feature.

PL

W tym badaniu zaprojektowano i wdrożono nowatorski binarny równoległy obwód powielający. Proponowany mnożnik jest połączeniem dwóch oddzielnych obwodów, a mianowicie obwodu mnożnika obciętego i obwodu najmniej znaczącego bitu (LSB). Mnożnik LSB został zaprojektowany w oparciu o matematyczne wyrażenie wedyjskie, ale wprowadzono pewne modyfikacje, aby był zgodny z mnożnikiem obciętym i aby uzyskać poprawne wyniki dla wszystkich wartości mnożenia. Zaprojektowany obwód jest kodowany w języku opisu sprzętu Verilog (HDL) przy użyciu Quartus II. Poziom transferu rejestrów jest weryfikowany, a poziom bramki jest symulowany przy użyciu platformy programowalnej macierzy bramek (FPGA) Cyclone IV. Proponowany mnożnik działa przy częstotliwości roboczej 107,5 MHz i wymaga 155 logik kombinacyjnych. Porównanie z innymi zgłoszonymi pracami pokazuje, że proponowany projekt ma 19,5% krótszy czas opóźnienia. Nowy powielacz równoległy nadaje się do zastosowań w różnych urządzeniach elektronicznych ze względu na swoją dobrą funkcję.

Słowa kluczowe

EN

parallel multiplier; truncated multiplier; LSB multiplier; Vedic expression

PL

mnożnik; LSB; równoległy obwód mnożący

• Wydawca: Wydawnictwo SIGMA-NOT
• Czasopismo: Przegląd Elektrotechniczny
• Rocznik: 2021
• Tom: R. 97, nr 7
• Strony: 19--22
• Opis fizyczny: Bibliogr. 26 poz., rys., tab.

Twórcy

autor

Alkurwy Salah Hasan Ibrahim

• College of Engineering, University of Diyala, 32001 Baqubah, Diyala, Iraq

• https://orcid.org/0000-0002-4495-0046

Bibliografia

• [1] A. D. BOOTH, "A Signed Binary Multiplication Technique," The Quarterly Journal of Mechanics and Applied Mathematics, vol. 4, no. 2, pp. 236–240, 1951.
• [2] H. L. G. a. C. W. S. J. Y. Lee, "A high-speed high-density silicon 8/spl times/8-bit parallel multiplier," IEEE Journal of Solid-State Circuits, vol. vol. 22, no. 1, pp. 35-40, Feb. 1987.
• [3] G. J. a. B. P. S. Gorgin, "Design and evaluation of decimal array multipliers," presented at the Conference Record of the Forty-Third Asilomar Conference on Signals, Systems and Computers, Pacific Grove, CA, 2009.
• [4] S. A. a. S. Chaturvedi, "HDL based implementation of N×N bitserial multiplier," presented at the 2014 International Conference on Signal Processing and Integrated Networks (SPIN), Noida, India, 2014.
• [5] L. P. Rubinfield, "A Proof of the Modified Booth's Algorithm for Multiplication," IEEE Transactions on Computers vol. C-24, no. 10, Oct. 1975 1975.
• [6] V. a. H. Bandeira, "A Two's Complement Array Multiplier Using True Values of the Operands," IEEE Transactions on Computers, vol. C-32, no. 8, pp. 745-747, Aug., 1983.
• [7] V. S. P. N. C. Madhulika, C. Prasanth and T. H. S. Praveen, "Design of systolic array multiplier circuit using reversible logic," presented at the 2017 2nd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT), Bangalore, India, 2017.
• [8] V. G. R. K. Yugandhar, M. Tejkumar and D. Siva, "High Performance Array Multiplier using Reversible Logic Structure," presented at the 018 International Conference on Current Trends towards Converging Technologies Coimbatore, India, 2018.
• [9] I. T. B. S. Srikanth, G. V. Priya and G. Usha, "Low power array multiplier using modified full adder," presented at the 2016 IEEE International Conference on Engineering and Technology (ICETECH), Coimbatore, India, 2016.
• [10] C. Wallace, "A suggestion for a fast multiplier," IEEE Transactions on Electronic Computers, vol. EC-13, no. 1, pp. 14–17, February . 1964.
• [11] S. R. a. K. Vanithamani, "Improvement of Wallace multipliers using parallel prefix adders," presented at the 2011 International Conference on Signal Processing, Communication, Computing and Networking Technologies, Thuckafay, 2011.
• [12] D. S. R. G. C. Ram, R. Balasaikesava and K. B. Sindhuri, "Design of delay efficient modified 16 bit Wallace multiplier," presented at the 016 IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT), Bangalore, India, 2016.
• [13] S. K. a. Y. S. S. Khan, "VLSI implementation of reduced complexity wallace multiplier using energy efficient CMOS full adder," presented at the 2013 IEEE International Conference on Computational Intelligence and Computing Research, Enathi, Enathi, India, 2013.
• [14] D. S. R. G. C. Ram, R. Balasaikesava and K. B. Sindhuri, "Design of delay efficient modified 16 bit Wallace multiplier," presented at the 2016 IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT), Bangalore, India, 2016.
• [15] S. N. a. R. V. V. D. Yaswanth, "Design and analysis of high speed and low area vedic multiplier using carry select adder," presented at the 2020 International Conference on Emerging Trends in Information Technology and Engineering (ic-ETITE), Vellore, India,, 2020.
• [16] S. N. M. B. Murugesh, J. Jayasree and G. V. K. Reddy, "Modified High Speed 32-bit Vedic Multiplier Design and Implementation," presented at the 2020 International Conference on Electronics and Sustainable Communication Systems (ICESC), Coimbatore, India, 2020.
• [17] Salah Alkurwy, Al-Azawi, Saad., Al Darraji, Nor., "FPGA Implementation of FIR Filter Design Based on Novel Vedic Multiplier," International Review on Modelling and Simulations (IREMOS), vol. 12, no. 2, pp. 66 - 71, 2019.
• [18] Salah Alkury, "A novel approach of multiplier design based on BCD decoder," Indonesian Journal of Electrical Engineering and Computer Science, vol. 14, no. 1, pp. 38 - 43, April 2019.
• [19] Y. L. a. Y. P. B. ZHU, "Pipelined Range Reduction Based Truncated Multiplier," Chinese Journal of Electronics, vol. 28, no. 6, pp. 1158-1164, 2019.
• [20] J. D. a. S. Li, "A Modular Multiplier Implemented With Truncated Multiplication," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 65, no. 11, pp. 1713-1717, Nov. 2018.
• [21] R. R. O. a. G. Rodríguez, "Truncated SIMD Multiplier Architecture for Approximate Computing in Low-Power Programmable Processors," IEEE Access, vol. 7, pp. 56353- 56366, 2019.
• [22] S. A. a. S. Chaturvedi, "Modified Binary Multiplier Circuit Based on Vedic Mathematics," presented at the 6th International Conference on Signal Processing and Integrated Networks (SPIN), Noida, India, 2019.
• [23] M. D. P. K. Pichhode, D. Shah, and B. Chaurasiya Rohit,, "FPGA implementation of efficient Vedic multiplier," presented at the 2015 International Conference on Information Processing, India, 2015.
• [24] H. G. a. S. Akhter, "VHDL implementation of fast multiplier based on Vedic mathematic using modified square root carry select adder," International Journal of Computer Applications, vol. 127, pp. 24 - 27, 2015.
• [25] M. P. R. K. Barik, and R. Panda, "Time efficient signed Vedic multiplier using redundant binary representation," Journal of Engineering,, vol. 2017, no. 3, pp. 60 - 68, 2017.
• [26] N. R. M. S. B. S. V. V. Shete, "Design and Comparison of Multiplier using Vedic Mathematics," presented at the 2016 International Conference on Inventive Computation Technologies (ICICT), Coimbatore, India, 2017.

Uwagi

Opracowanie rekordu ze środków MNiSW, umowa Nr 461252 w ramach programu "Społeczna odpowiedzialność nauki" - moduł: Popularyzacja nauki i promocja sportu (2021).