FPGA realization of an improved alpha max plus beta min algorithm

• Autorzy: Czyżak M. , Smyk R.
• Konferencja: Computer Applications in Electrical Engineering 2014 (28-29.04.2014; Poznań, Polska)
• Języki publikacji: EN

Abstrakty

EN

The improved version of the alpha max plus beta min square-rooting algorithm and its realization in the Field Programmable Gate Array (FPGA) are presented. The algorithm computes the square root to calculate the approximate magnitude of a complex sample. It is especially useful for pipelined calculations in the DSP. The improved version allows to reduce the peak error from about 4% to 0.33%. This is attained by determination of the approximate ratio of arguments and adequate selection of algorithm coefficients. Four approximation regions are used and hence four sets of coefficients. Also a Xilinx FPGA implementation for 12-bit sign magnitude numbers is shown.

Słowa kluczowe

EN

square root computation; alpha max plus beta min algorithm; field programmable gate array (FPGA)

• Wydawca: Wydawnictwo Politechniki Poznańskiej
• Czasopismo: Poznan University of Technology Academic Journals. Electrical Engineering
• Rocznik: 2014
• Tom: No. 80
• Strony: 151--160
• Opis fizyczny: Bibliogr. 11 poz., rys., tab.

Twórcy

autor

Czyżak M.

• Gdansk University of Technology

autor

Smyk R.

• Gdansk University of Technology

Bibliografia

• [1] Parhami B., Computer Arithmetic: Algorithms and Hardware Designs, Oxford University Press, 2000.
• [2] Zurawski J.H.P, Gosling J.B.: Design of a high-speed root, multiply and divide unit, IEEE Trans. on Computers, Volume.34, Number 1, pp. 13-23, 1985.
• [3] Majerski S.: Square-root algorithms for high-speed digital circuits, IEEE Trans. on Computers, Volume 34, Number 8, pp. 1016-1024, 1985.
• [4] Hashemian R.: Square rooting algorithms for integer and floating-point numbers. IEEE Trans. on Computers, Volume 39, Number 8, pp. 1025-1029, 990.
• [5] Montushi P., Mezzalama M.: Survey of square-rooting algorithms. Proc. IEEE, pt. E, Volume 137, pp. 31-40, 1990.
• [6] Ciminera L., Montushi P.: High-radix square rooting, IEEE Trans. on Computers, Volume 39, Number 10, pp. 1220-1231, 1990.
• [7] Ercegowac M.D., Lang T.: Division and square-root: Digit recurrence algorithms and implementations, Kluwer 1994.
• [8] Sutikno T.: An efficient implementation of the nonrestoring square root algorithm in gate level, International Journal of Computer Theory and Engineering, Volume 3, Number 1, pp. 46-51, 2011.
• [9] Sutikno, Jidin A.Z., Jidin A., Idris N.R.N.: Simplified VHDL Coding of modified nonrestoring square root calculator, International Journal of Reconfigurable and Embedded Systems, Volume 1, Number 1, pp. 37-42, 2012.
• [10] Filip A.E.: Linear approximations to √x² + Y² having equiripple characteristics. IEEE Trans. on Audio and Electroacoustics, Volume AU-21, Number 6, pp. 554-556, 1973.
• [11] Xilinx, Virtex-7, www.xilinx.com.