On configuration of residue scaling process in pipelined radix-4 MQRNS FFT processor

• Autorzy: Smyk R. , Czyżak M.
• Konferencja: Computer Applications in Electrical Engineering 2014 (28-29.04.2014; Poznań, Polska)
• Języki publikacji: EN

Abstrakty

EN

Residue scaling is needed in pipelined FFT radix-4 processors based on the Modified Quadratic Residue Number System (MQRNS) at the output of each butterfly. Such processor uses serial connection of radix-4 butterflies. Each butterfly comprises n subunits, one for each modulus of the RNS base and generates four complex residue numbers. In order to prevent the arithmetic overflow in the succesive stage, every number has to be scaled, i.e. divided by a certain constant. The dynamic range of the processed signal increases due to the summation within the butterfly and the transformation of coefficients of the FFT algorithm to integers. The direct approach would require eight residue scalers that would be highly ineffective regarding that such a set of scalers had to be placed after each butterfly. We show and analyze a structure which uses parallel-to-serial transformation of groups of numbers so that only two scalers are needed.

Słowa kluczowe

EN

fast Fourier transform; residue number system; modified quadratic residue number system; FFT pipelined processor

• Wydawca: Wydawnictwo Politechniki Poznańskiej
• Czasopismo: Poznan University of Technology Academic Journals. Electrical Engineering
• Rocznik: 2014
• Tom: No. 80
• Strony: 145--150
• Opis fizyczny: Bibliogr. 8 poz., rys., tab.

Twórcy

autor

Smyk R.

• Gdansk University of Technology

autor

Czyżak M.

• Gdansk University of Technology

Bibliografia

• [1] Oppenheim A.V., Schafer R.W., Discrete-Time Signal Processing, Third Edition, Prentice-Hall, 2009.
• [2] Soderstrand M.A. et al, Residue Number System Arithmetic: Modern Applications in Digital Signal Processing, IEEE Press, Piscataway, NJ, 1986.
• [3] Rabiner L.R., Gold B., Theory and Application of Digital Signal Processing. Prentice-Hall 1975.
• [4] Krishnan R., Jullien G.A., Miller W.C., The modified quadratic residue number system (MQRNS) for complex high-speed signal processing, IEEE Transactions on Circuits and Systems, Volume 33, Number 3, Pages 325-327, 1986.
• [5] Czyżak M., Smyk R., Radix-4 DFT butterfly realization with the use of the modified quadratic residue number system, Poznan University of Technology Academic Journals, Electrical Engineering, Number 63, Pages 39-51, 2010.
• [6] Shousheng H., Torkelson M., A new approach to pipeline FFT processor, Proceedings of the 10th International Parallel Processing Symposium IPPS '96, Pages 766-770, 1996.
• [7] Wold E., Despain A., Pipeline and parallel-pipeline FFT processors for VLSI implementations, IEEE Transactions on Computers, Volume C-33, Number 5, Pages 414-426, May 1984.
• [8] Czyżak M., Smyk R., Ulman Z., Pipelined scaling of signed residue numbers with the mixed-radix conversion in the programmable gate array. Poznan University of Technology Academic Journals. Electrical Engineering, Number 76, Pages 89-99, 2013.