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Administration-and communication-aware IP core mapping in scalable multiprocessor system-on-chips via evolutionary computing

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Warianty tytułu
Języki publikacji
EN
Abstrakty
EN
In this paper, an efficient mapping of intellectual property (IP) cores onto a scalable multiprocessor system-on-chip with a k-ary 2-mesh network-on-chip is performed. The approach is to place more affine IP cores closer to each other reducing the number of traversed routers. Affinity describes the pairwise relationship between the IP cores quantified by an amount of exchanged communication or administration data. A genetic algorithm (GA) and a mixed-integer linear programming (MILP) solution use the affinity values in order to optimize the IP core mappings. The GA generates results faster and with a satisfactory quality relative to MILP. Realistic benchmark results demonstrate that a tradeoff between administration and communication affinity significantly improves application performance.
Rocznik
Strony
133--146
Opis fizyczny
Bibliogr. 17 poz., rys.
Twórcy
autor
  • Vodafone Chair Mobile Communications Systems Technische Universitat Dresden, 01062 Dresden, Germany
autor
  • Vodafone Chair Mobile Communications Systems Technische Universitat Dresden, 01062 Dresden, Germany
autor
  • Vodafone Chair Mobile Communications Systems Technische Universitat Dresden, 01062 Dresden, Germany
Bibliografia
  • [1] S. Borkar, “Thousand core chips: a technology perspective,” in Proc. of DAC, 2007, pp. 746–749.
  • [2] P. Guerrier and A. Greiner, “A generic architecture for on-chip packet-switched interconnections,” in Proc. of DATE, 2000, pp. 250–256.
  • [3] A. Hemani, A. Jantsch, S. Kumar, A. Postula, J. Oberg, M. Millberg, and D. Lindquist, “Network ¨on a chip: An architecture for billion transistor era,” in Proc. of NorChip, 2000.
  • [4] J. Balfour and W. J. Dally, “Design tradeoffs for tiled cmp on-chip networks,” in Proc. of ICS, 2006,pp. 187–198.
  • [5] H. Esbensen and E. Kuh, “Design space explorationusing the genetic algorithm,” in Proc. of ISCAS,1996, pp. 500–503.
  • [6] G. Ascia, V. Catania, and M. Palesi, “Multiobjective mapping for mesh-based noc architectures,” in Proc. of CODES, ser. CODES+ISSS, 2004, pp. 182–187.
  • [7] O. Ozturk and D. Demirbas, “Heterogeneous network-on-chip design through evolutionary computing,” International Journal of Electronics, vol. 97, no. 10, pp. 1139–1161, 2010.
  • [8] K. Latif, A.-M. Rahmani, T. Seceleanu, and H. Tenhunen, “Power- and performance-aware ip mapping for noc-based mpsoc platforms,” in Proc. of ICECS, dec. 2010, pp. 758–761.
  • [9] X. Wang, M. Yang, Y. Jiang, and P. Liu, “A poweraware mapping approach to map ip cores onto nocs under bandwidth and latency constraints,” ACM Trans. Archit. Code Optim., vol. 7, pp. 1:1–1:30, May 2010.
  • [10] B. Ristau, T. Limberg, O. Arnold, and G. Fettweis, “Dimensioning heterogeneous MPSoCs via parallelism analysis,” in Proc. of DATE, 2009, pp. 554–557.
  • [11] C. Puttmann, J.-C. Niemann, M. Porrmann, and U. Ruckert, “Giganoc - a hierarchical network-onchip for scalable chip-multiprocessors,” in Proc. ofEuromicro, 2007, pp. 495–502.
  • [12] F. Gilabert, S. Medardoni, D. Bertozzi, L. Benini,M. E. Gomez, P. Lopez, and J. Duato, “Exploring high-dimensional topologies for noc designthrough an integrated analysis and synthesis framework,”in Proc. of NOCS, 2008, pp. 107–116.
  • [13] B. Ristau, T. Limberg, and G. Fettweis, “A mapping framework based on packing for design space exploration of heterogeneous mpsocs,” J. Signal Process. Syst., vol. 57, pp. 45–56, Oct 2009.
  • [14] M. Wall. (2011, Sep.) Galib: A c++ library of genetic algorithm components. [Online]. Available: http://lancet.mit.edu/ga/
  • [15] IBM. (2011, Sep.) Ibm ilogcplex optimizer. [Online]. Available:http://www.ibm.com/software/integration/optimization/cplex-optimizer/
  • [16] R. Dick. (2011, Sep.) Embedded system synthesis benchmarks suite. [Online]. Available:http://ziyang.eecs.umich.edu/∼dickrp/e3s/
  • [17] EEMBC. (2011, Sep.) The embedded microprocessor benchmark consortium. [Online]. Available:http://www.eembc.org/
Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-4ac28aab-dfc8-4972-ad86-539c73224740
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