PL EN


Preferencje help
Widoczny [Schowaj] Abstrakt
Liczba wyników
Tytuł artykułu

Low power 9-bit pipelined A/D and 8-bit self-calibrated D/A converters for a DSP system

Treść / Zawartość
Identyfikatory
Warianty tytułu
Języki publikacji
EN
Abstrakty
EN
A low power, low voltage current mode 9 bit pipelined a/d converter and 8 bit self-calibrated d/a converter to interface a DSP system are presented in the paper. The a/d converter is built of 1.5 bit stages with digital error correction logic. The d/a converter is composed of 3 LSBs fine and 5 MSBs coarse current mode converters. The a/d and d/a converters were designed in 0.35 μm technology, then fabricated to verify the proposed concept. The performances of both converters are compared to the performances of known converter structures. The main advantages of the proposed converters are low power consumption and small chip area.
Rocznik
Strony
979--988
Opis fizyczny
Bibliogr. 23 poz., rys., diag., tab.
Twórcy
autor
  • Faculty of Electronics and Information Science, Koszalin University of Technology, 2. Sniadeckich St. 75-453 Koszalin, Poland
autor
  • Faculty of Electronics and Information Science, Koszalin University of Technology, 2. Sniadeckich St. 75-453 Koszalin, Poland
Bibliografia
  • [1] O.A. Horna, “A 150 Mbps A/D and D/A conversion system”, Comsat Technical Review 2, 52-57 (1972).
  • [2] K. Wawryn, R. Suszyński, and B. Strzeszewski, “A low power low voltage current-mode a/d and d/a converters for DSP system”, Proc. 53rd IEEE Int. Midwest Symp. on Circuit and Systems 1, CD-ROM (2011).
  • [3] K. Wawryn, R. Suszyński, and B. Strzeszewski, “A low power digitally error corrected 2.5 bit per stage pipelined a/d con- verter using current-mode signals”, J. Circuits, Systems and Computers 20, 29-43 (2011).
  • [4] K.Wawryn, R. Suszyński, and B. Strzeszewski. “Current Mode Pipelined A/D Converter”, Proc. IEEE Design & Technology of Integrated Systems 1, CD-ROM (2008).
  • [5] Jian Li, Xiaoyang Zeng, Jianyun Zhang, Lei Xie, H. Deng, and Yawei Guo, “Design of an ADC for subsampling video applications”, Analog Integrated Circuits and Signal Processing 49, 303-312 (2006).
  • [6] O.A Adeniran and A. Demosthenous, “An ultra-energyefficient wide-bandwidth video pipeline adc using optimized architectural partitioning”, IEEE Trans. on Circuits and Systems 53, 2485-2497 (2006).
  • [7] B. Palomo, F. Munoz, R.G. Carvajal, J.R. Garcia, and F. Marquez, “An 8-bit 19MS/s low-power 0.35 μm CMOS pipelined ADC for DVB-H”, Integration, VLSI J. 45, 222-227 (2012).
  • [8] Yuh-Shyan Hwang, Jiann-Jong Chen, Sing-Yen Wu, Lu-Po Liao, and Chia-Chun Tsai, “A new pipelined analog-to-digital converter using current conveyors”, Analog Integrated Circuits and Signal Processing 50, 213-220 (2007).
  • [9] Qi Yu, Xiang-zhan Wang, Ning Ning, Lin Tang, Hong-Bin Li, and Mo-hua Yang, “A 10-bit 100MSPS 0.35 μm Si CMOS Pipeline ADC”, Proc. 7th Int. Conf. on Solid-State and Integrated Circuits Technology 2, 1523-1525 (2004).
  • [10] P.Malcovati, L. Picolli, L. Crespi, F. Chaahoub, and A. Baschirotto, “A 90-nm CMOS, 8-bit pipeline ADC with 60-MHz bandwidth and 125-MS/s or 250-MS/s sampling frequency”, Analog Integrated Circuits and Signal Processing (64), 159-172 (2010).
  • [11] J. Hu, N. Dolev, and B. Murmann, “A 9.4-bit, 50-MS/s, 1.44-mW pipelined ADC using dynamic residue amplification”, IEEE Symp. VLSI Circuits Dig. Tech. Papers 1, 216-217 (2008).
  • [12] M. Yoshioka, M. Kudo, T. Mori, and S. Tsukamoto, “A 0.8 V 10 b 80 MS/s 6.5 mW pipelined ADC with regulated overdrive voltage biasing”, IEEE ISSCC Dig. Tech. Papers 1, 452-453 (2007).
  • [13] M. Boulemnakher, E. Andre, J. Roux, and F. Paillardet, “A 1.2 V 4.5mW 10 b 100 MS/s pipeline ADC in a 65 nm CMOS”, IEEE ISSCC Dig. Tech. Papers 1, 250-251 (2008).
  • [14] H. Hernandez, W. Van Noije, E. Roaandand, and J. Navarro, “A small area 8 bits 50 MHz CMOS DAC for Bluetooth transmitter”, Analogue Integrated Circuits and Signal Processing 57, 69-77 (2008).
  • [15] J. Huang, Y. He, Y. Sun, H. Liu, and H. Yang, “A 10-bit 200- MHz CMOS video DAC for HDTV applications”, Analogue Integrated Circuits and Signal Processing 52, 133-138 (2007).
  • [16] H. Wang, H. Kao, and T. Lee, “An 8-bit 2-V 2-mW 0.25-mm2 CMOS DAC”, IEEE Asia Conf. on Advanced System Integrated Circuits 1, 102-105 (2004).
  • [17] H.H. Cho, C.Y. Park, and G.S. Yune, “A 10-bit 210-MHz CMOS D/A converter for WLAN”, Proc. Asia-Pacific Conf. on Advanced System Integrated Circuits 1, 106-109 (2004).
  • [18] Y. Zhou and J. Yuan, “An 8-Bit 100-MHz CMOS linear interpolation DAC”, IEEE J. Solid-State Circuits 38, 1758-1761 (2010).
  • [19] S. Sarkar, R.S. Prasad, S.K. Dey, V. Belde, and S. Banerjee, “An 8-bit 1.8 V 500 MS/s CMOS DAC with a novel four-stage current steering architecture”, IEEE Int. Symp. on Circuits and Systems 1, 149-152 (2008).
  • [20] Y. Zhou and J. Yuan, “An 8-bit 100-MHz low glitch interpolation DAC”, IEEE Int. Symp. on Circuits and Systems 1, 116-119 (2001).
  • [21] T. Hsin-Wen, C. Soon-Jyh, and H. Su-Ling, “A Design of Linearity Built-in Self-Test for Current-Steering DAC”, J. Electronic Testing 27, 85-94 (2011).
  • [22] N.C. Battersby and C. Toumazou, “Class AB switched-current memory for analogue sampled data systems”, Electronics Letters 27, 873-875 (1991).
  • [23] N.C. Battersby and C. Toumazou, Class AB Switched Current Techniques, Switched-Currents an Analogue Technique for Digital Technology, eds. C. Toumazou, J.B. Hughes, and N.C. Battersby, Peter Peregrinus Ltd., New York, 1993.
Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-4a5cda0b-efcf-4852-90de-51d2fa30c81e
JavaScript jest wyłączony w Twojej przeglądarce internetowej. Włącz go, a następnie odśwież stronę, aby móc w pełni z niej korzystać.