Power-aware scheduling of data-flow hardware circuits with symbolic control

• Autorzy: Özbaltan Mete , Berthier Nicolas

Identyfikatory

DOI

10.24425/acs.2021.137426

• Języki publikacji: EN

Abstrakty

EN

We devise a tool-supported framework for achieving power-efficiency of data-flow hardware circuits. Our approach relies on formal control techniques, where the goal is to compute a strategy that can be used to drive a given model so that it satisfies a set of control objectives. More specifically, we give an algorithm that derives abstract behavioral models directly in a symbolic form from original designs described at Register-transfer Level using a Hardware Description Language, and for formulating suitable scheduling constraints and power-efficiency objectives. We show how a resulting strategy can be translated into a piece of synchronous circuit that, when paired with the original design, ensures the aforementioned objectives. We illustrate and validate our approach experimentally using various hardware designs and objectives.

Słowa kluczowe

EN

symbolic discrete controller synthesis; digital synchronous circuits; power efficiency

• Wydawca: Polish Academy of Sciences, Committee of Automatic Control and Robotics
• Czasopismo: Archives of Control Sciences
• Rocznik: 2021
• Tom: Vol. 31, No. 2
• Strony: 431--446
• Opis fizyczny: Bibliogr. 19 poz., rys., tab., wzory

Twórcy

autor

Özbaltan Mete

• Erzurum Technical University, Erzurum, Turkey

autor

Berthier Nicolas

• University of Liverpool, Liverpool, England

Bibliografia

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Uwagi

Opracowanie rekordu ze środków MNiSW, umowa Nr 461252 w ramach programu "Społeczna odpowiedzialność nauki" - moduł: Popularyzacja nauki i promocja sportu (2021).