An Improvement of CMOS Voltage Reference

• Autorzy: Punyawong W. , Sa-Ngiamvibool W. , Aurasopon A. , Hongprasit S.

Warianty tytułu

PL

Ulepszone źródło napięcia wzorcowego w technologii CMOS

• Języki publikacji: EN

Abstrakty

EN

This paper presents a CMOS voltage reference design, which is widely used in electronic circuits, both analog and digital circuits. In the conventional, a CMOS voltage reference circuit design composed of several MOS transistors and complicated circuits, the output voltage cannot be adjusted to any levels. Therefore, in this paper proposed the CMOS voltage reference circuit design technique based on current combination circuit, which it was reduced number of MOS transistors and the proposed circuit is able to operate without complex startup circuit. The performance of the proposed circuit is confirmed through PSPICE simulation results, the circuit can be operated with supply voltage varies from 1.85 - 4 V, the output voltage reference is about 500±2.5 mV at wide temperature range of -58 oC to 120°C, it has very low temperature coefficient of about 61.19 ppm/ °C, and low power dissipation is 5.51 μW.

PL

W artykule opisano ulepszone źródło napięcia wzorcowego w technologii CMOS. W ulepszonej technologii wykorzystuje się mniej tranzystorów a możliwość ustawiania napięcia jest bardziej uniwersalna niż w typowych układach tego typu.

Słowa kluczowe

EN

temperature compensation; CMOS; voltage reference; weak inversion

PL

źródło napięcia wzorcowego; CMOS; uniwersalność

• Wydawca: Wydawnictwo SIGMA-NOT
• Czasopismo: Przegląd Elektrotechniczny
• Rocznik: 2013
• Tom: R. 89, nr 6
• Strony: 109--112
• Opis fizyczny: Bibliogr. 16 poz., rys., tab., wykr.

Twórcy

autor

Punyawong W.

• Mahasarakham University

autor

Sa-Ngiamvibool W.

• Mahasarakham University

autor

Aurasopon A.

• Mahasarakham University

autor

Hongprasit S.

• Rajamangala University of Technology Isan KhonKaen Campus

Bibliografia

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