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Universal Address Sequence Generator for Memory Built-in Self-test

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Warianty tytułu
Języki publikacji
EN
Abstrakty
EN
This paper presents the universal address sequence generator (UASG) for memory built-in-self-test. The studies are based on the proposed universal method for generating address sequences with the desired properties for multirun march memory tests. As a mathematical model, a modification of the recursive relation for quasi-random sequence generation is used. For this model, a structural diagram of the hardware implementation is given, of which the basis is a storage device for storing so-called direction numbers of the generation matrix. The form of the generation matrix determines the basic properties of the generated address sequences. The proposed UASG generates a wide spectrum of different address sequences, including the standard ones, such as linear, address complement, gray code, worst-case gate delay, 2i, next address, and pseudorandom. Examples of the use of the proposed methods are considered. The result of the practical implementation of the UASG is presented, and the main characteristics are evaluated.
Wydawca
Rocznik
Strony
41--61
Opis fizyczny
Bibliogr. 50 poz., rys., tab.
Twórcy
  • Bialystok University of Technology, Bialystok, Poland
  • Gymnasium, Darmstadt, Germany
  • Belarusian State University of Informatics and Radioelectronics, Minsk, Belarus
Bibliografia
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  • [38] Yarmolik VN, Yarmolik SV. The repeated nondestructive march tests with variable address sequences. Automation and Remote Control. 2007;68(4):688-698.
  • [39] Yarmolik SV, Yarmolik VN. Modified Gray And Counter Sequences For Memory Test Address Generation. In: Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006. Gdynia, Poland; 2006. p. 572-576.
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  • [41] Yarmolik VN, Sokol B, Yarmolik SV. Counter Sequences for Memory Test Address Generation. In: Proceedings of the 12th International Conference Mixed Design of Integrated Circuits and Systems. MIXDES’05. Krakow, Poland: IEEE Computer Society; 2005. p. 413-418.
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  • [45] Yarmolik VN, Yarmolik SV. Address sequences for multi run RAM testing (In Russ.). Informatics. 2014; (2):124-136.
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  • [47] Yarmolik SV, Yarmolik VN. Memory Address Generation for Multiple Run march Tests with Different Average Hamming Distance. In: Proceedings of the IEEE East-West Design and Test Workshop. EWDTW’06. Sochi, Russia; 2006. p. 212-216.
  • [48] Mrozek I, Yarmolik VN. Multiple Controlled Random Testing. Fundamenta Informaticae. 2016;144(1): 23-43.
  • [49] Mrozek I, Yarmolik VN. Two-Run RAM March Testing with Address Decimation. Journal of Circuits, Systems, and Computers. 2017;26(2):1750031. Available from: http://dx.doi.org/10.1142/S0218126617500311. doi:10.1142/S0218126617500311.
  • [50] Liu H, Chen TY. Randomized Quasi-Random Testing. IEEE Transactions on Computers. 2016 June;65(6):1896-1909. doi:10.1109/TC.2015.2455981.
Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-46a6c5c5-c4a2-4acc-bb95-9ebb5bf6e114
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