On simplification of residue scaling process in pipelined Radix-4 MQRNS FFT processor

• Autorzy: Smyk R. , Czyżak M.
• Języki publikacji: EN

Abstrakty

EN

Residue scaling is needed in pipelined FFT radix-4 processors based on the Modified Quadratic Residue Number System (MQRNS) at the output of each butterfly. Such processor uses serial connection of radix-4 butterflies. Each butterfly comprises n subunits, one for each modulus of the RNS base and generates four complex residue numbers. In order to prevent arithmetic overflow intermediate results after each butterfly have to be scaled, i.e. divided by a certain constant. The number range of the processed signal increases due to transformation of coefficients of the FFT algorithm to integers and summation and multiplication within the butterfly. The direct approach would require eight residue scalers that would be highly ineffective regarding that such a set of scalers had to be placed after each butterfly. We show and analyze a structure which uses parallel-to-serial transformation of groups of numbers so that only two residue scalers are needed.

Słowa kluczowe

EN

fast Fourier transform; residue number system; modified quadratic residue number system; pipelined FFT processor

• Wydawca: Wydawnictwo Politechniki Poznańskiej
• Czasopismo: Computer Applications in Electrical Engineering
• Rocznik: 2014
• Tom: Vol. 12
• Strony: 588--596
• Opis fizyczny: Bibliogr. 16 poz., rys., tab.

Twórcy

autor

Smyk R.

• Gdańsk University of Technology 80-233 Gdańsk, ul. G. Narutowicza 11/12

autor

Czyżak M.

• Gdańsk University of Technology 80-233 Gdańsk, ul. G. Narutowicza 11/12

Bibliografia

• [1] Rabiner L.R., Gold B.: Theory and Application of Digital Signal Processing. Prentice-Hall 1975.
• [2] Oppenheim A.V., Schafer R.W.: Discrete-Time Signal Processing, Third Edition. Prentice-Hall, 2009.
• [3] Brigham E.O.: The Fast Fourier Transform and Its Applications. Prentice-Hall, Upper Saddle River, NJ, 1988.
• [4] Swartzlander Jr. E.E.: Systolic FFT processors: A Personal Perspective. Journal of Signal Processing Systems, Number 53, 2008, Pages 3 - 14.
• [5] Texas Instruments, TI C66x, http://www.ti.com .
• [6] Analog Devices: TigerSHARC processor benchmarks. http://www.analog.com/en/content/tigersharc_benchmarks/fca.html, October 2014.
• [7] Analog Devices, ADSP-214xx SHARC® Processor Hardware Reference, http://www.analog.com/static/imported-files/processor_manuals/ADSP-214xx_hwr_rev1.1.pdf, Apil 2013.
• [8] Soderstrand M.A. et al.: Residue Number System Arithmetic: Modern Applications in Digital Signal Processing. IEEE Press, Piscataway, NJ, 1986.
• [9] Krishnan R., Jullien G.A., Miller W.C.: The modified quadratic residue number system (MQRNS) for complex high-speed signal processing. IEEE Transactions on Circuits and Systems, Volume 33, Number 3, Pages 325 - 327, 1986.
• [10] Ulman Z., Czyżak M.: Highly parallel, fast scaling of numbers in nonredundant residue arithmetic. IEEE Trans. on Signal Processing, Volume 45, Number 2, 1998, Pages 487 - 496.
• [11] Czyżak M., Smyk R., Ulman Z.: Pipelined scaling of signed residue numbers with the mixed-radix conversion in the programmable gate array. Poznan University of Technology Academic Journals. Electrical Engineering, Number 76, Pages 89 - 99, 2013.
• [12] Czyżak M., Smyk R.: Radix-4 DFT butterfly realization with the use of the modified quadratic residue number system. Poznan University of Technology Academic Journals, Electrical Engineering, Number 63, Pages 39 - 51, 2010.
• [13] Shousheng H., Torkelson M.: A new approach to pipeline FFT processor. Proceedings of the 10th International Parallel Processing Symposium IPPS '96, Pages 766 - 770, 1996.
• [14] Wold E., Despain A.: Pipeline and parallel-pipeline FFT processors for VLSI implementations, IEEE Transactions on Computers, Volume C-33, Number 5, Pages 414 - 426, May 1984.
• [15] Shousheng H., Torkelson M., Shousheng H., Torkelson M., Designing Pipeline FFT processor for OFDM (de)modulation, Signals, Systems, and Electronics, 1998. ISSSE 98, 1998 URSI International Symposium on, Pages 257 - 262, 29 Sep - 2 Oct 1998.
• [16] Wenqi L., Xuan W., Xiangran S.: Design of Fixed-Point High-Performance FFT Processor, 2010 2nd International Conference on Education Technology and Computer (ICETC), Volume 5, Pages V5-139 - V5-143, June 22-24, 2010.