Implementation of Algorithm of Petri Nets Distributed Synthesis into FPGA

• Autorzy: Bukowiec A. , Tkacz J. , Gratkowski T. , Gidlewicz T.

Identyfikatory

DOI

10.2478/eletel-2013-0038

• Języki publikacji: EN

Abstrakty

EN

In the paper an implementation of algorithm of Petri net array-based synthesis is presented. The method is based on decomposition of colored interpreted macro Petri net into subnets. The structured encoding of places in subnets is done of using minimal numbers of bits. Microoperations, which are assigned to places, are written into distributed and flexible memories. It leads to realization of a logic circuit in a twolevel concurrent structure, where the combinational circuit of the first level is responsible for firing transitions, and the second level memories are used for generation of microoperations. This algorithm is implemented in C# and delivered as a stand alone library.

Słowa kluczowe

EN

C#; decomposition; FGPA; logic synthesis; Petri net

• Wydawca: Polish Academy of Sciences, Committee of Electronics and Telecommunication
• Czasopismo: International Journal of Electronics and Telecommunications
• Rocznik: 2013
• Tom: Vol. 59, No. 4
• Strony: 317--324
• Opis fizyczny: Bibliogr. 36 poz., wykr.

Twórcy

autor

Bukowiec A.

• Institute of Computer Engineering and Electronics, University of Zielona Góra, Licealna 9, 65-417 Zielona Góra, Poland

autor

Tkacz J.

• Institute of Computer Engineering and Electronics, University of Zielona Góra, Licealna 9, 65-417 Zielona Góra, Poland

autor

Gratkowski T.

• Institute of Computer Engineering and Electronics, University of Zielona Góra, Licealna 9, 65-417 Zielona Góra, Poland

autor

Gidlewicz T.

• Institute of Computer Engineering and Electronics, University of Zielona Góra, Licealna 9, 65-417 Zielona Góra, Poland

Bibliografia

• [1] N. Chang, W. H. Kwon, and J. Park, “Hardware implementation of real-time Petri-net-based controllers,” Control Engineering Practice, vol. 6, no. 7, pp. 889-895, 1998. [Online]. Available: http://www.sciencedirect.com/science/article/pii/S0967066198000768.
• [2] N. Marranghello, J. Mirkowski, and K. Bilinski, “Synthesis of synchronous digital systems specified by Petri nets,” in Hardware Design and Petri Nets, A. Yakovlev, L. Gomes, and L. Lavagno, Eds. Boston: Kluwer Academic Publishers, 2000, pp. 129-150. [Online]. Available: http://link.springer.com/chapter/10.1007%2F978-1-4757-3143-9_7.
• [3] B. W. Bomar, “Implementation of microprogrammed control in FPGAs,” IEEE Transactions on Industrial Electronics, vol. 49, no. 2, pp. 415-422, 2002. [Online]. Available: http://ieeexplore.ieee.org/xpl/freeabs all.jsp?arnumber=993275.
• [4] D. Drusinsky and D. Harel, “Using statecharts for hardware description and synthesis,” IEEE Transactions on Computer-Aided Design, vol. 8, no. 7, pp. 798-807, 1989. [Online]. Available: ieeexplore.ieee.org/xpl/freeabs all.jsp?arnumber=31537.
• [5] L. Gomes and A. Costa, “From use cases to system implementation: Statechart based co-design,” in Proceedings of 1st ACM & IEEE Conference on Formal Methods and Programming Models for Codesign MEMOCODE’03. Mont Saint-Michel, France: IEEE Computer Society Press, 2003, pp. 24-33. [Online]. Available: ieeexplore.ieee.org/xpl/freeabs all.jsp?arnumber=1210083.
• [6] G. Łabiak, “From UML statecharts to FPGA - the HiCoS approach,” in Proceedings of the Forum on Specification & Design Languages FDL’03. Frankfurt, Germany: ECSI, 2003, pp. 354-363.
• [7] M. Doligalski, “Behavioral specification diversification for logic controllers implemented in FPGA devices,” in Proceedings of the Annual FPGA Conference, ser. FPGAworld’12. New York, USA: ACM, 2012, pp. 6:1–6:5. [Online]. Available: http://dl.acm.org/citation.cfm?doid=2451636.2451642.
• [8] T. Murata, “Petri nets: Properties, analysis and applications,” Proceedings of the IEEE, vol. 77, no. 4, pp. 541–580, 1989. [Online]. Available: http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=24143.
• [9] A. Karatkevich, Dynamic Analysis of Petri Net-Based Discrete Systems, ser. Lecture Notes in Control and Information Sciences. Berlin: Springer-Verlag, 2007, vol. 356. [Online]. Available: http://link.springer.com/book/10.1007%2F978-3-540-71560-3.
• [10] T. Kozłowski, E. Dagless, J. Saul, M. Adamski, and J. Szajna, “Parallel controller synthesis using Petri nets,” IEE Proceedings – Computers and Digital Techniques, vol. 142, no. 4, pp. 263-271, 1995. [Online]. Available: http://digitallibrary.theiet.org/content/journals/10.1049/ip-cdt 19951886.
• [11] M. Minoux and K. Barkaoui, “Deadlocks and traps in Petri nets as Horn-satisfiability solutions and some related polynomially solvable problems,” Discrete Applied Mathematics, vol. 29, no. 2-3, pp. 195-210, December 1990. [Online]. Available: http://dl.acm.org/citation.cfm?id=108745.108751.
• [12] J. Esparza and M. Silva, “On the analysis and synthesis of free choice systems,” in Advances in Petri Nets 1990, ser. Lecture Notes in Computer Science, G. Rozenberg, Ed. Berlin/Heidelberg: Springer-Verlag, 1991, vol. 483, pp. 243-286. [Online]. Available: http://link.springer.com/chapter/10.1007%2F3-540-53863-1_28.
• [13] K. Barkaoui and J.-F. Pradat-Peyre, “On liveness and controlled siphons in Petri nets,” in Application and Theory of Petri Nets, ser. Lecture Notes in Computer Science, J. Billington and W. Reisig, Eds. Berlin/Heidelberg: Springer, 1996, vol. 1091, pp. 57-72. [Online]. Available: http://link.springer.com/chapter/10.1007%2F3-540-61363-3_4.
• [14] L. A. Cortés, P. Eles, and Z. Peng, “Modeling and formal verification of embedded systems based on a Petri net representation,” Journal of Systems Architecture, vol. 49, no. 12-15, pp. 571-598, 2003. [Online]. Available: http://dl.acm.org/citation.cfm?id=967630.
• [15] C. Girault and R. Valk, Petri Nets for System Engineering: A Guide to Modeling, Verification, and Applications. Berlin/Heidelberg: Springer-Verlag, 2003. [Online]. Available: http://www.springer.com/computer/swe/book/978-3-540-41217-5.
• [16] A. Karatkevich and T. Gratkowski, “Analysis of the operational Petri nets by a distributed system,” in Proceedings of the International Conference on Modern Problems of Radio Engineering, Telecommunications and Computer Science TCSET’04, Lviv Polytechnic National University. Lviv, Ukraine: Lviv, Publishing House of Lviv Polytechnic, 2004, pp. 319-322. [Online]. Available: ieeexplore.ieee.org/xpl/freeabs all.jsp?arnumber=1365973.
• [17] A. Węgrzyn, “Parallel algorithm for computation of deadlocks and traps in Petri nets,” in 10th IEEE International Conference Emering Technologies and Factory Automation ETFA’05, vol. 1, Universita di Catania. Catania, Italy: Piscataway, IEEE Operation Center, 2005, pp. 143-148. [Online]. Available: http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=1612513.
• [18] K. Biliński, M. Adamski, J. Saul, and E. Dagless, “Petri-net-based algorithms for parallel-controller synthesis,” IEE Proceedings – Computers and Digital Techniques, vol. 141, no. 6, pp. 405-412, 1994. [Online]. Available: ieeexplore.ieee.org/xpl/freeabs all.jsp?arnumber=331627.
• [19] E. Soto and M. Pereira, “Implementing a Petri net specification in a FPGA using VHDL,” in Design of Embedded Control Systems, M. Adamski, A. Karatkevich, and M. Węgrzyn, Eds. New York: Springer, 2005, pp. 167–174. [Online]. Available: http://link.springer.com/chapter/10.1007%2F0-387-28327-7_14.
• [20] L. Gomes, A. Costa, J. Barros, and P. Lima, “From Petri net models to VHDL implementation of digital controllers,” in 33rd Annual Conference of the IEEE Industrial Electronics Society IECON’07. Taipei, Taiwan: IEEE, 2007, pp. 94–99. [Online]. Available: http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=4460403.
• [21] M. Węgrzyn and A. Węgrzyn, “Penlogic – system for concurrent logic controllers design,” in Design of Digital Systems and Devices, ser. Lecture Notes in Electrical Engineering, M. Adamski, A. Barkalov, and M. Węgrzyn, Eds. Berlin: Springer-Verlag, 2011, vol. 79, pp. 215-228. [Online]. Available: http://link.springer.com/chapter/10.1007%2F978-3-642-17545-9_9.
• [22] M. Adamski and M. Węgrzyn, “Petri nets mapping into reconfigurable logic controllers,” Electronics and Telecommunications Quarterly, vol. 55, no. 2, pp. 157-182, 2009.
• [23] T. Łuba, M. Rawski, and Z. Jachna, “Functional decomposition as a universal method of logic synthesis for digital circuits,” in Proceedings of the 9th International Conference Mixed Design of Integrated Circuits and Systems MixDes’02, Wrocław, Poland, 2002, pp. 285-290.
• [24] A. Bukowiec and A. Barkalov, “Structural decomposition of finite state machines,” Electronics and Telecommunications Quarterly, vol. 55, no. 2, pp. 243-267, 2009.
• [25] A. Bukowiec, Synthesis of Finite State Machines for FPGA devices based on Architectural Decomposition, ser. Lecture Notes in Control and Computer Science. Zielona Góra: University of Zielona Góra Press, 2009, vol. 13.
• [26] A. Bukowiec and M. Adamski, “Synthesis of Petri nets into FPGA with operation flexible memories,” in Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits and Systems DDECS’12, Tallinn, Estonia, 2012, pp. 16-21. [Online]. Available: http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6219016.
• [27] Synthesis of macro Petri nets into FPGA with distributed memories, International Journal of Electronics and Telecommunications, vol. 58, no. 4, pp. 403-410, 2012. [Online]. Available: http://www.degruyter.com/view/j/eletel.2012.58.issue-4/v10177-012-0055-x/v10177-012-0055-x.xml.
• [28] K. Jensen, K. Kristensen, and L. Wells, “Coloured Petri nets and CPN tools for modelling and validation of concurrent systems,” International Journal on Software Tools for Technology Transfer (STTT), vol. 9, no. 3, pp. 213-254, 2007. [Online]. Available: http://link.springer.com/article/10.1007%2Fs10009-007-0038-x.
• [29] M. Adamski and J. Tkacz, “Formal reasoning in logic design of reconfigurable controllers,” in 11th IFAC/IEEE International Conference on Programmable Devices and Embedded Systems PDeS 2012, Z. Bradáč, F. Bradáč, and F. Zezulka, Eds., Brno, Czech Republic, 2012, pp. 1–6. [Online]. Available: http://www.ifacpapersonline.net/Detailed/57207.html.
• [30] A. Karatkevich, “On macroplaces in Petri nets,” in Proceedings of IEEE East-West Design & Test Symposium EWDTS’08. Lviv, Ukraine: IEEE, 2008, pp. 418-422. [Online]. Available: http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=5580151.
• [31] A. Węgrzyn, “On decomposition of Petri net by means of coloring,” in Proceedings of IEEE East-West Design & Test Workshop EWDTW’06, Sochi, Russia, 2006, pp. 407-413.
• [32] J. Tkacz, “State machine type colouring of Petri net by means of using a symbolic deduction method,” Measurement Automation and Monitoring, vol. 53, no. 5, pp. 120-122, 2007. [Online]. Available: http://www.pak.info.pl/index.php?menu=artykulSzczegol&idArtykul=401.
• [33] S. Brown and Z. Vernesic, Fundamentals of Digital Logic with VHDL Design, 2nd ed. New York: McGraw-Hill, 2005. [Online]. Available: http://highered.mcgraw-hill.com/sites/0073380334/.
• [34] G. Borowik, M. Rawski, G. Łabiak, A. Bukowiec, and H. Selvaraj, “Efficient logic controller design,” in Fifth International Conference on Broadband and Biomedical Communications IB2Com’10, Malaga, Spain, 2010, pp. 1-6. [Online]. Available: http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=5723633.
• [35] G. Łabiak, M. Adamski, M. Doligalski, J. Tkacz, and A. Bukowiec, “UML modelling in rigorous design methodology for discrete controllers,” International Journal of Electronics and Telecommunications, vol. 58, no. 1, pp. 27-34, 2012. [Online]. Available: http://www.degruyter.com/view/j/eletel.2012.58.issue-1/v10177-012-0004-8/v10177-012-0004-8.xml.
• [36] M. Doligalski, “Behavioral specification of the logic controllers by means of the hierarchical configurable Petri nets,” in 11th IFAC/IEEE International Conference on Programmable Devices and Embedded Systems PDeS 2012, Z. Bradáč, F. Bradáč, and F. Zezulka, Eds., Brno, Czech Republic, 2012, pp. 87-90. [Online]. Available: http://www.ifac-papersonline.net/Detailed/57239.html.