Interconnections coupling through substrate for frequencies up to 100 GHz

• Autorzy: Gerakis V , Hatzopoulos A.
• Języki publikacji: EN

Abstrakty

EN

This work presents a study on the substrate noise coupling between two interconnects. A highly, a lightly and a uniformly doped substrate, approximating most modern technologies, are described. The three different doping profiles are simulated for various interconnect distances and different metal layers assuming a 65 nm bulk CMOS technology. A proper data analysis methodology is presented, including z and s parameters extraction and de-embedding procedure.

Słowa kluczowe

EN

substrate noise; interconnect coupling; substrate doping; S-parameters; Z-parameters

PL

zakłócenia podłożowe; domieszkowanie substratu; parametry rozproszenia; parametry impedancji

• Wydawca: Lodz University of Technology. Department of Microelectronics and Computer Science
• Czasopismo: International Journal of Microelectronics and Computer Science
• Rocznik: 2014
• Tom: Vol. 5, nr 4
• Strony: 144--148
• Opis fizyczny: Bibliogr. 12 poz.

Twórcy

autor

Gerakis V

• Department of Electrical and Computer Engineering. Aristotle University of Thessaloniki, Thessaloniki, Greece

autor

Hatzopoulos A.

• Department of Electrical and Computer Engineering. Aristotle University of Thessaloniki, Thessaloniki, Greece

Bibliografia

• [1] Jyh-Chyum Guo and Yi-Min Lin, “A New Lossy Substrate De-embedding Method for Sub-100 nm RF CMOS Noise Extraction and Modeling” in IEEE Transactions on electron devices, Vol. 53, N02, February 2006, pp. 339-347.
• [2] Ahmed Helmy, Mohammed Ismail, “Substrate noise coupling in RFICs”, Analog Circuits and Signal Processing series, Springer,2008.
• [3] Wen Shu, Sam Shichijo and Rashaunda M. Henderson, "Loss Mechanism and High-low Doping Profile Effects of Silicon Substrate with Different Resistivities at High Frequency", Microwave Symposium Digest (HVIS), 2013 IEEE MTT-S International, pp. 1-4.
• [4] Hai Lan, Zhiping Yu and Robert W. Dutton, “A CAD-Oriented Modeling Approach of Frequency-Dependent Behavior of Substrate Noise Coupling for Mixed-Signal IC Design” in Proceedings of the 4th Intemational Symposium on Quality Electronic Design (ISQED'03), 2003, pp. 195-200.
• [5] Gholan Reza Karimi and Ebrahim Akbari, “An efficient technique for accurate modeling and simulation of substrate coupling in deep micron mixed-signal ICs”, International Conference on Electronic Devices, Systems and Applications (ICEDSA2010), 2010, pp. 88-92.
• [6] Harpreet Parashar and Ghanshyam Singh, “Effects of capacitive and inductive coupling on interconnects at RF Frequencies”, Devices and Communications (ICDeCom), 2011 International Conference, pp. 1-5.
• [7] Ajit Sharma, Patrick Birrer, Sasi Kumar Arunachalam, Chenggang Xu, Teri S. Fiez, Kartikeya Mayaram, “Accurate prediction of substrate parasitics in heavily doped CMOS processes using a calibrated boundary element solver”, IEEE Transactions on Very Large Scale Integration (VLSI) systems, vol. 13, No. 7, Jyly 2005, pp. 843-851.
• [8] Madhumanti Datta, Susmita Sahoo, Rajib Kar, "Bandwidth Modelling for Distributed On-Chip RLCG Interconnect Considering Coupling Effects", International Conference on Devices and iCommunications (ICDECom), 2011,pp. 1-5.
• [9] Georgios Veronis, Yi-Chang Lu, and Robert W. Dutton,"Modeling of Wave Behavior of Substrate Noise Coupling for Mixed-Signal IC Design", Proceedings of the 5th International Symposium on Quality Electronic Design, 2004, pp 303-308.
• [10] Maria Drakaki, Alkis A. Hatzopoulos, Stylianos Siskos, "Improving the Accuracy of the De-embedding Methods for on-wafer RF Measurements", Elsevier Science Publishers, Microelectronics Journal, Volume 40, Issue 6, June, 2009,pp. 958-965.
• [11] Luuk F. Tiemeijer and Ramon J. Havens, "A Calibrated Lumped-Element De-Embedding Technique for On-Wafer RF Characterization of High-Quality Inductors and High-Speed Transistors", IEEE Transactions on electron devices, vol. 50, no. 3, pp. 822-829, Mar. 2003.
• [12] E. P. Vandamme, D. M. M.-P. Schreurs, and C. van Dinther, “Improved three-step de-embedding method to accurately account for the influence of pad parasitics in silicon on-wafer RF test-structures”, IEEE Transactions on electron devices, vol. 48, no. 4, pp. 737-742, Apr. 2001.