Optimized implementation of lattice Boltzmann method in ARUZ

• Autorzy: Jabłoński Grzegorz , Kupis Joanna
• Języki publikacji: EN

Abstrakty

EN

The paper presents the optimized implementation of the Lattice Boltzmann method on ARUZ, a massively parallel FPGA-based simulator located in Lodz, Poland. Compared to previous publications, a performance improvement of 46% has been achieved on D2Q9 lattice due to overlapping of communication with computation. The presented approach is suitable also for other cellular automata-based simulations. Extrapolation of results from the single ARUZ board suggests, that LBM simulation of 1080 × 480 lattice on 18 panels of ARUZ would reach the performance of 302 · 10³ MLUPS (Million Lattice Updates per Second). This implementation has been compared to the classical supercomputer solution, giving much better power efficiency (3000 MLUPS/kW vs. 1280 MLUPS/kW, respectively).

Słowa kluczowe

EN

distributed system; reconfigurable system; FPGA; Lattice Boltzmann Method; ARUZ

PL

system rozproszony; FPGA; metoda siatkowa Boltzmanna; ARUZ; Analizator Rzeczywistych Układów Złożonych

• Wydawca: Lodz University of Technology. Department of Microelectronics and Computer Science
• Czasopismo: International Journal of Microelectronics and Computer Science
• Rocznik: 2018
• Tom: Vol. 9, nr 2
• Strony: 79--84
• Opis fizyczny: Bibliogr. 10 poz.

Twórcy

autor

Jabłoński Grzegorz

• Department of Microelectronics and Computer Science, Lodz University of Technology, ul. Wólczańska 221/223, 90-924 Lódź, Poland

autor

Kupis Joanna

• Department of Microelectronics and Computer Science, Lodz University of Technology, ul. Wólczańska 221/223, 90-924 Lódź, Poland

Bibliografia

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