Design of high-performance PFD-CP for 403MHz CMOS fractional-N frequency synthesizer

• Autorzy: Saleh S. , Hamdy G. , Elsemary H. , Zaki A.
• Języki publikacji: EN

Abstrakty

EN

This brief discusses the challenges and employs a novel charge-pump and a PFD/CP linearization technique to improve the performance of a 403MHz fractional-N PLL. Techniques are proposed to improve the linearity of the PLL by forcing the PFD/CP to operate in a linear part of its transfer characteristics, while the charge-pump minimizes the current mismatch between the up and down currents by using feedback. The circuit is designed in 0.13jim CMOS process and consumes a total power of 2.6mW. The simulation results show that the synthesizer has a phase noise of-128dBc/Hz at 1MHz offset.

Słowa kluczowe

EN

N-PLL; charge pump; current matching; PFD/CP

PL

N-PLL; pompa zasilająca; dokładność prądowa; PFD/CP

• Wydawca: Lodz University of Technology. Department of Microelectronics and Computer Science
• Czasopismo: International Journal of Microelectronics and Computer Science
• Rocznik: 2017
• Tom: Vol. 8, nr 3
• Strony: 97--100
• Opis fizyczny: Bibliogr. 5 poz., rys., wykr.

Twórcy

autor

Saleh S.

• Department of Microelectronics, Electronics Research Institute - ER1, Al-Tahrir Street, Dokki, Giza, Egypt

autor

Hamdy G.

• Department of Microelectronics, Electronics Research Institute - ER1, Al-Tahrir Street, Dokki, Giza, Egypt

autor

Elsemary H.

• Department of Microelectronics, Electronics Research Institute - ER1, Al-Tahrir Street, Dokki, Giza, Egypt

autor

Zaki A.

• Department of Microelectronics, Electronics Research Institute - ER1, Al-Tahrir Street, Dokki, Giza, Egypt

Bibliografia

• [1] H. Wang, G. Shou, and N. Wu, "An adaptive frequency synthesizer architecture reducing reference sidebands," IEEE Internationals Symposium on Circuits and Systems, 2006.
• [2] K. Lakshmikumar, "Analog PLL Design With Ring Oscillators at Low-Gigahertz Frequencies in Nanometer CMOS: Challenges and Solutions," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 56, no. 5, pp. 389-393, May 2009.
• [3] J.-S. Lee, M.-S. Keel, S.-I. Lim, and S. Kim, "Charge pump with perfect current matching characteristics in phase-locked loops," Electronics Letters, vol. 36, no. 23, pp. 1907-1908, Nov 2000.
• [4] K. Wang, A. Swaminathan, and I. Galton, "Spurious-Tone Suppression Techniques Applied to a Wide-Bandwidth 2.4GHz Fractional-N PLL," IEEE International Conference on Solid-State Circuits, ISSCC, pp. 342-618, Feb. 2008.
• [5] C. Charles et el., "A Calibrated Phase/Frequency Detector for Reference Spur Reduction in Charge-Pump PLLs," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 53, no. 9, pp. 822 -826, Sep 2006.

Uwagi

Opracowanie rekordu w ramach umowy 509/P-DUN/2018 ze środków MNiSW przeznaczonych na działalność upowszechniającą naukę (2018).