Analysis and investigation of Schottky barrier MOSFET current injection with process and device simulation

Schwarz, Mike; Calvet, Laurie E.; Snyder, John P.; Krauss, Tillmann; Schwalke, Udo; Kloes, Alexander

Artykuł - szczegóły

Tytuł artykułu

Analysis and investigation of Schottky barrier MOSFET current injection with process and device simulation

Autorzy

Schwarz Mike , Calvet Laurie E. , Snyder John P. , Krauss Tillmann , Schwalke Udo , Kloes Alexander

Treść / Zawartość

Pełne teksty:

Schwarz_et_al_analysis_ IJoMaCS_1_2018.pdf

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Warianty tytułu

Języki publikacji

Abstrakty

In this paper we focus on the implementation of a process flow of SB-MOSFETs into the process simulator of the Synopsys TCAD Sentaurus tool-chain. An improved structure containing topography is briefly discussed and further device simulations are applied with the latest physical models available. Key parameters are discussed and finally the results are compared with fabricated SB-MOSFETs in terms of accuracy and capability of process simulations.

Słowa kluczowe

Poisson equation device simulation field emission modeling MOSFET process simulation Schottky barrier Synopsys TCAD thermionic emission tunneling current

równanie Poissona emisja polowa modelowanie symulacja procesu bariera Schottky'ego Synopsys TCAD emisja termoelektronowa prąd tunelowy

Wydawca

Lodz University of Technology. Department of Microelectronics and Computer Science

Czasopismo

International Journal of Microelectronics and Computer Science

Rocznik

2018

Tom

Vol. 9, nr 1

Strony

1--8

Opis fizyczny

Bibliogr. 21 poz.

Twórcy

autor

Schwarz Mike

mike.schwarz1980@googlemail.com

NanoP, Technische Hochschule Mittelhessen, Germany

autor

Calvet Laurie E.

Université Paris-Sud, France

autor

Snyder John P.

JCap, LLC, USA

autor

Krauss Tillmann

TU Darmstadt, Germany

autor

Schwalke Udo

TU Darmstadt, Germany

autor

Kloes Alexander

NanoP, Technische Hochschule Mittelhessen, Germany

Bibliografia

[1] J. Bruner, ”Intel 22nm 3-D Tri-Gate Transistor Technology”, News release and press materials (Intel), http://www.intel.com, 2011.
[2] Q. Liu, et al., ”High performance UTBB FDSOI devices featuring 20nm gate length for 14nm node and beyond”, IEDM, Washington DC, USA, 2013.
[3] TSMC, ”TSMC Website: Dedicated Foundry - Technology”, http://www.tsmc.com/english/dedicatedFoundry/technology, 2018.
[4] Global Foundries, ”Global Foundries Website: Technology Solutions”, https://www.globalfoundries.com/technology-solutions, 2018.
[5] J. M. Larson, J. P. Snyder, ”Overview and status of metal S/D Schottkybarrier MOSFET technology”, IEEE Transaction Electron Devices 53 (5), 1048–1058, 2006.
[6] W. E. Purches, A. Rossi, R. Zhao, S. Kafanov, T. L. Duty, A. S. Dzurak, S. Rogge, and G. C. Tettamanzi, ”A planar Al-Si Schottky barrier metal-oxide-semiconductor field effect transistor operated at cryogenic temperatures, Applied Physics Letters 107, 2015.
[7] J. P. Snyder, ”Benefits of Schottky Barrier MOS vs. Conventional Doped S/D MOS”, Meeting on Schottky Barrier devices, Ueberherrn, Germany, 2016.
[8] S. M. Sze, KWOG K. NG, ”Physics of Semiconductor Devices”, John Wiley & Sons, 2007.
[9] J. L. Padilla, L. Knoll, F. G´amiz, Q. T. Zhao, A. Godoy, and S. Mantl, ”Simulation of Fabricated 20-nm Schottky Barrier MOSFETs on SOI: Impact of Barrier Lowering”, IEEE Transaction Electron Devices 59 (5), 1320–1327, 2012.
[10] M. Schwarz, L. E. Calvet, J. P. Snyder, T. Krauss, U. Schwalke, and A. Kloes, ”On the Physical Behavior of Cryogenic IV and III-V Schottky Barrier MOSFET Devices”, IEEE Transaction Electron Devices 64 (9), 3808–3815, 2017.
[11] M. Fritze, C. L. Chen, S. Calawa, D. Yost, B. Wheeler, P. Wyatt, C. L. Keast, J. Snyder, and J. Larson, ”High-speed Schottky-barrier pMOSFET with fT = 280GHz”, IEEE Electron Device Letters 25 (4), 220–222, 2004.
[12] ”TCAD Sentaurus”, Synopsys, Inc., c-2016.12 Edition, 2016.
[13] M. Kumar, S. Haldar, M. Gupta, R.S. Gupta, ”Physics based analytical model for surface potential and subthreshold current of cylindrical Schottky Barrier gate all around MOSFET with high-k gate stack”, Superlattices and Microstructures 90, 215–226, 2016.
[14] M. Schwarz, A. Kloes, ”Analysis and Performance Study of III-V Schottky Barrier Double-Gate MOSFETs Using a 2-D Analytical Model”, IEEE Transactions on Electron Devices 63 (7), 2757–2763, 2016.
[15] A.F. Tasch, H. Shin, C.Park, J. Alvis, and S. Novak, ”An Improved Approach to Accurately Model B and BF2 Implants in Silicon”, J. Electrochem. Soc., 136, p.810, 1989.
[16] M. Schwarz, L. E. Calvet, J. P. Snyder, T. Krauss, U. Schwalke, and A. Kloes, ”Process and Device Simulation of Schottky Barrier MOSFETs for Analysis of Current Injection”, in Proc. MIXDES, Gydnia, Poland, 2018.
[17] K.M. Klein, C. Park, A.F. Tasch, R.B. Simonton, and S. Novak, ”Analysis of Implanted Boron Distribution Dependence on Tilt and Rotation Angle”, J. Electrochem. Soc., 138, p.2102, 1991.
[18] C.Park, K.M. Klein, A.F. Tasch, R.B. Simonton, S. Novak, and G. Lux, ”A Comprehansive and Computationally Efficient Modeling Strategy for Simulation of Boron Ion Implantation into Single-Crystal Silicon with Explicit Dose and Implant Angle Dependence”, COMPEL, 10, p.331, 1991).
[19] G. Zhu, X. Zhou, T.S. Lee, L.K. Ang, G.H. See, S. Lin, Y.-K. Chin, and K.L. Pey, ”A Compact Model for Undoped Silicon-Nanowire MOSFETs With Schottky-Barrier Source/Drain”, IEEE Transactions on Electron Devices 56 (5), 1100–1109, 2009.
[20] S. Kale, and P.N. Kondekar, ”Suppression of ambipolar leakage current in Schottky barrier MOSFET using gate engineering”, Electronics Letters 51 (19), 1536–1538, 2015.
[21] L. E. Calvet, ”Electrical Transport in Schottky Barrier MOSFETs”, PhD Thesis, Yale University, USA, 2001.

Uwagi

Opracowanie rekordu w ramach umowy 509/P-DUN/2018 ze środków MNiSW przeznaczonych na działalność upowszechniającą naukę (2019).

Typ dokumentu

Bibliografia

Identyfikator YADDA

bwmeta1.element.baztech-3f1f7ba0-df2c-47e9-8683-923f028a875d