Recursive PLL of the First Order

• Autorzy: Perlić D. , Žorić A. , Babić D. , Perlić D.

Warianty tytułu

PL

Rekursyjna pętla synchronizacji fazowej PLL pierwszego rzędu

• Języki publikacji: EN

Abstrakty

EN

This paper describes a new type of Recursive Phase Locked Loop (PLL) of the first order. The PLL is a linear discrete system described by two recursive equations. The hardware implementation of PLL is described. Different analyses of PLL parameters are made. Computer simulation of PLL is introduced in order to give better insight into the PLL characteristics and to confirm the mathematical analyses, too. Made analysis shows that PLL is suitable for different applications. Precise digital phase shifting of pulse rate is one of the applications which is described. The picture of the input and output pulse rates, recorded on the simulated PLL by professional software package “Multisim”, is presented.

PL

Opisano nowy typ rekurencyjnej pętli synchronizacji fazowej (PLL). Przedstawiono różne metody analizy układu oraz symulację komputerową. Opisano możliwość precyzyjnego cyfrowego przesunięcia fazowego impulsów.

Słowa kluczowe

EN

phase locked loop; discrete linear system; recursive algorithm

PL

układ PLL; rekursyjna pętla fazowa PLL

• Wydawca: Wydawnictwo SIGMA-NOT
• Czasopismo: Przegląd Elektrotechniczny
• Rocznik: 2013
• Tom: R. 89, nr 7
• Strony: 50--53
• Opis fizyczny: Bibliogr. 15 poz., rys.

Twórcy

autor

Perlić D.

• Slobomir P University-Bosnia and Herzegovina

autor

Žorić A.

• Faculty of Technical Science in Kosovska Mitrovica-Serbia

autor

Babić D.

• Slobomir P University-Bosnia and Herzegovina
• [e-mail]

autor

Perlić D.

• Slobomir P University-Bosnia and Herzegovina

Bibliografia

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• [2] Dj. Perišić, A. Žorić, S. Obradović, P. Spalević, Application of Frequency Locked Loop in Consumption Peak Load Control, Electrical Review, ISSN 0033-2097, R.88 NR 1b/2012, Page 264-267.
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• [7] C. C. Chung, An all-digital phase-locked loop for high speed clock generation, IEEE Journal of Solid-State Circuits, 2003, Vol. 38, Issue 2, Page 347-359.
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• [10] Giovani Bianchi, “Phase-Locked Loop Synthesizer Simulation“, Nc-Hill, Inc. New York, USA, 2005.
• [11] Roland E. Best, Phase Locked Loops, Mc Graw Hill, ISBN 0- 07-141201-8, 2003, P. 421.
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• [13] Gardner F. M., “Phaselock tecniques“, Hoboken, Wiley- Interscience, 2005.
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