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Tytuł artykułu

A robust synchronization method for grid sequence extraction

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Wybrane pełne teksty z tego czasopisma
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Warianty tytułu
PL
Algorytm synchronizacji częstotliwościowej w ekstrakcji składowych symetrycznych w sieci
Języki publikacji
EN
Abstrakty
EN
A robust synchronization method based on least mean square is proposed for the real time detection of fundamental and harmonic symmetrical components, including positive, negative and zero sequence. The new architecture is composed of three parallel structures providing estimation of each phase fundamental and harmonic components delivered into a linear matrix transformation for grid sequence extraction. To achieve frequency adaptation, a combination of least mean square and phase locked loop is used. The paper presents excellent simulation and experimental results in order to verify correctness and validity of the algorithm.
PL
W artykule opisano opracowaną metodę synchronizacji z siecią, wykrywającą w czasie rzeczywistym częstotliwość podstawową oraz wyższe harmoniczne, w tym składową zgodną, przeciwną i zerową. Architektura składa się z trzech równoległych estymatorów harmonicznych dla każdej fazy. Po przetworzeniu danych i wyznaczeniu składowych, dokonywana jest synchronizacja, z wykorzystaniem metody najmniejszych kwadratów oraz PLL. Przedstawione zostały wyniki symulacyjne i eksperymentalne.
Rocznik
Strony
101--109
Opis fizyczny
Bibliogr. 32 poz., schem., tab., wykr.
Twórcy
autor
  • Department of Electrical Engineering, Harbin Institute of Technology, Harbin 150001
autor
  • Department of Electrical Engineering, Harbin Institute of Technology
autor
  • Department of Electrical Engineering, Harbin Institute of Technology
autor
  • Department of Electrical Engineering, Harbin Institute of Technology
autor
  • Department of Electrical Engineering, Harbin Institute of Technology
Bibliografia
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  • [24] P. Rodriguez, R. Teodorescu, I. Candela, A. Timbus, M. Liserre, and F. Blaabjerg, New positive-sequence voltage detector for grid synchronization of power converters under faulty grid conditions, the 37th IEEE Power Electronics Specialists Conference ~PESC’ 2006~, June 18-22, 2006, Jeju, Korea.
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Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-3c7c060a-2312-4a0c-94f8-bbab30ba1589
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