Synteza automatu Moore’a z wbudowanym blokiem pamięci w strukturach programowalnych

• Autorzy: Kołopieńczyk M. , Barkalov A. , Titarenko L.

Warianty tytułu

EN

EMB-based synthesis of Moore FSM

• Języki publikacji: PL

Abstrakty

PL

W artykule zostanie przedstawiona metoda umożliwiająca syntezę skończonego automatu stanów typu Moore’a z wbudowanym blokiem pamięci (ang. Embedded Memory Blocks, EMB) w strukturach programowalnych typu FPGA (ang. Field Programmable Gate Array, FPGA). Zaproponowana metoda bazuje na kodowaniu pewnej wybranej części zbioru warunków logicznych przez dodatkowe zmienne. W artykule zostanie zaprezentowany przykład projektowania układu.

EN

The model of the Moore finite state machine (FSM) is very often used for representing a control unit [1]. Nowadays, two classes of programmable logic devices: complex programmable logic devices (CPLD) and field-programmable gate arrays (FPGA) are used for implementing logic circuits of FSMs [2, 3]. This paper deals with FPGA-based Moore FSMs. It is very important to use EMBs in the logic design. It leads to decreasing in both the number of interconnections and chip area occupied by an FSM logic circuit. In turn, it results in decrease in the propagation time as well as the consumed power of a circuit [9]. A lot of methods for implementing an FSM logic circuit with RAMs are known [10 – 19]. For rather complex FSMs, the method of replacement of logical conditions [20] is used. In this case, optimization efforts target hardware reduction for the multiplexer executing the replacement. In this paper we propose a method based on existence of pseudoequivalent states of the Moore FSM for solving this problem [21]. The method is based on replacement of some part of the set of logical conditions by additional variables. It results in diminishing the number of LUTs in the multiplexer used for replacement of logical conditions. To represent a control algorithm, the language of graph-schemes of algorithms [20] is used. An example of application of the proposed design method is given.

Słowa kluczowe

PL

Moore FSM; RAM; wbudowane bloki pamięci; projektowanie; układy logiczne

EN

Mealy FSM; FPGA; embedded memory block; design; logic circuit

• Wydawca: Wydawnictwo PAK
• Czasopismo: Pomiary Automatyka Kontrola
• Rocznik: 2013
• Tom: R. 59, nr 8
• Strony: 776--780
• Opis fizyczny: Bibliogr. 20 poz., rys., tab., wzory

Twórcy

autor

Kołopieńczyk M.

• Uniwersytet Zielonogórski, Licealna 9, 65-417 Zielona Góra

autor

Barkalov A.

• Uniwersytet Zielonogórski, Licealna 9, 65-417 Zielona Góra

autor

Titarenko L.

• Uniwersytet Zielonogórski, Licealna 9, 65-417 Zielona Góra

Bibliografia

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