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Identification of Circuit Parameters for the Specified or Measured Performances

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Języki publikacji
EN
Abstrakty
EN
Extension of the method of analog circuit parameter identification for the specified design performances, originally presented by the same author in 1982, is described. These parameters are designated by means of PSpice simulation of the adjoint circuit to the original one. In this adjoint circuit, elements of the original circuit, described by the sized parameters, are replaced by controlled sources. Each such source is controlled by the differential voltage or current, difference between the calculated voltage or current and the specified one, with infinitely large gain. The method is applicable to both linear and nonlinear DC circuits and AC circuits and can be used in many fields of analog circuit design, such as: finding of acceptability region, analog fault diagnosis, postproduction identification and tuning. In the later cases, design performances are replaced by measurements of Circuit Under Test (CUT). Simplicity, extremely low computational complexity and high accuracy are the main benefits of the proposed, basic Circuit Theory based, approach - the solution is found after a single PSpice simulation. For better understanding of the presented methodology, five practical examples are discussed.
Twórcy
autor
  • Institute of Electronics, Silesian University of Technology, Akademicka 16, 44-100 Gliwice, Poland
Bibliografia
  • [1] O.V. Abramov, D.A. Nazarov, “Regions of Acceptability Approximation in Reliability Design”, Reliability: Theory and Aplications, Vol. 7, No. 3, pp. 43-49, 2012.
  • [2] A. Macura, J. Rutkowski, “New Method of Approximating the Acceptable Region of Nonlinear Resistive Networks”, Electronic Letters, Vol.18, No.15, pp. 654-656, 1982.
  • [3] F. Grasso, S. Manetti, M.C. Piccirilli, “A Method for Acceptability Region Representation in Analogue Linear Networks”, International Journal of Circuit Theory and Applications, Vol.37, No.10, pp. 1051-1061, 2008.
  • [4] R. Hashemian, “Fixator-Norator Pairs Versus Direct Analytical Tools in Performing Analog Circuit Designs”, IEEE Transactions on CAS II, Vol. 61, No 8, pp.569-573, 2014.
  • [5] R. Hashemian, “Application of Fixator-Norator Pairs in Designing Active Loads and Current Mirrors in Analog Integrated Circuits,” IEEE Transactions on Very Large Scale Integrated (VLSI) Systems, Vol. 20, No.12, pp. 2220-2231, 2012.
  • [6] R. M. J. McPherson, “Chapter 7. Ventilation Network Analysis” in Subsurface Ventilation and Environmental Engineering, Germany, Springer, 1993.
  • [7] P. Kumar, K. Duraiswamy, “An Optimized Device Sizing of Analog Circuits using Particle Swarm Optimization”, Journal of Computer Science, Vol.8, No.6, pp. 930-935, 2012.
  • [8] P. Kumar, K. Duraiswamy, A.J. Anand, “An Optimized Device Sizing of Analog Circuits using Genetic Algorithm, European Journal of Scientific Research, vol. 69, no. 3, pp. 441-448, 2012.
  • [9] M. Barari, H.R. Karimi, F. Razaghian, “Analog Circuit Design Optimization Based on Evolutionary Algorithms”, Mathematic Problems in Engineering, http://www.hindawi.com/journals/mpe/2014/593684/, 2014.
  • [10] T. Golonek, J. Rutkowski, “Genetic Algorithm Based Method for Optimal Analog Test Point Selection”, IEEE Transactions on CAS II, Vol. 54, No 2, pp.117-121, 2007.
  • [11] J.W. Bandler, A.E. Salama, “Fault Diagnosis in Analog Circuits”, Proceedings of the IEEE, Vol. 73, Issue 8, pp. 1279-1325, 1985.
  • [12] V. Sharma, A. Verma, “Fault Diagnosis of Analog Circuits Using dc Approach”, International Journal of Engineering and Advanced Technology, Vol.2, Issue 5, pp. 60-64, 2013.
  • [13] “Advanced Circuit Analysis and Exploration with Circuit Parameters in NI Multisim”, National Instruments, http://www.ni.com/white-paper/14831/en/, 2013. A. B. Author, “Book style with paper title and editor,”in Title, 1nd ed. vol. 1, C. Editor, Ed. City: Publisher, 1999, pp. 10-50.
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Bibliografia
Identyfikator YADDA
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