Realization of Multi-Operand Modular Adders in the FPGA technology

• Autorzy: Czyżak M. , Smyk R.
• Konferencja: Computer Applications in Electrical Engineering 2012 (23-24.04.2012; Poznań, Polska)
• Języki publikacji: EN

Abstrakty

EN

The paper presents the design and realization of the Multi-Operand Modular Adder (MOMA) structures in the Xilinx FPGA environment with the use of the Virtex 6 technology. The design is based on the LUTs(26x 1) that simulate small RAMs which serve as the main component for the look-up realization of addition and modulo generation. In this paper the MOMAs for modular addition of five-bit operands are shown. In the paper first the general structures of the MOMAs are considered and next two approaches to the multi-operand modulo addition are examined. Both approaches make use of the four-operand MOMAs. In the first approach, the four-operand MOMA is based on the two-operand modular adders, whereas in the second approach initially the four operand binary addition is performed, in the next stage followed by the modulo reduction. The implementation of both MOMA types is shown and analyzed with respect to hardware amount and pipelining frequency.

Słowa kluczowe

EN

Multi-Operand Modular Adders; MOMA; FPGA; TOMA; FOMA

• Wydawca: Wydawnictwo Politechniki Poznańskiej
• Czasopismo: Poznan University of Technology Academic Journals. Electrical Engineering
• Rocznik: 2012
• Tom: No. 71
• Strony: 217--223
• Opis fizyczny: Bibliogr. 10 poz., rys.

Twórcy

autor

Czyżak M.

• Gdansk University of Technology

autor

Smyk R.

• Gdansk University of Technology

Bibliografia

• [1] Szabo N.S. and Tanaka R.J., Residue Arithmetic and its Applications to Computer Technology, New York, McGraw-Hill, 1967.
• [2] Soderstrand M. et al., Residue Number System Arithmetic: Modern Applications in Digital Signal Processing, IEEE Press, NY, 1986.
• [3] Omondi A., Premkumar B., Residue Number Systems: Theory and Implementation, London, Imperial College Press, 2007.
• [4] Piestrak S.J., Design of residue generators and multioperand modulo adders using carry-save adders, IEEE Trans. Comp., Volume 43, Pages 68-77, Jan. 1994.
• [5] Alia G., Martinelli E., Designing multi-operand modular adders, Electronic Letters, Volume 32, No. 1, Jan. 1996.
• [6] Smyk R., Czyżak M., Design and realization of two-operand modular adders in the FPGA, Poznan University of Technology, Academic Journals, Electrical Engineering (this issue).
• [6] Alia G., Martinelli E., VLSI binary-residue converters for pipelined processing, Computer J., Volume 33, No.5, Pages 473-475, 1990.
• [7] Premkumar A.B., A formal framework for conversion from binary to residue numbers, IEEE Trans. Circuits and Systems-II, Volume 49, No. 2, Feb. 2002, Pages 135-144.
• [8] Czyżak M., High-speed binary-to-residue converter with improved architecture, 27th Int. Conf. on Fundamentals of Electrotechnics and Circuit Theory, Gliwice-Niedzica, May 26-29, 2004, Pages 431-436.
• [9] www.xilinx.com, 7 Series FPGAs Overview, ds 180 (v1.9) January 15, 2012.

Uwagi

Błędna numeracja bibliografii.